TSMC (NYSE: TSM) In-Depth Investment Research Report

Report Version: v2.0 (Full Version)
Target Company: Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM)
Analysis Date: 2026-02-10
Data Cut-off: FY2025 Q4 (December 2025)
Analyst: Investment Research Agent (Tier 3 Institutional-Grade In-Depth Research)

Table of Contents

Part A · Introduction

• Chapter 1 · Executive Summary
• Chapter 2 · Market Attention Radar and Non-Consensus View

Part B · Understanding the Company

• Chapter 3 · Company Panorama Profile
• Chapter 4 · Industry Chain Panorama Mapping
• Chapter 5 · Precise Positioning in the AI Supercycle
• Chapter 6 · In-Depth Analysis of Technology Node Competitiveness
• Chapter 7 · Customer Concentration Risk Analysis
• Chapter 8 · Moat Quantification and Competitive Matrix

Part C · Financials and Valuation

• Chapter 9 · Six-Layer Cycle Radar
• Chapter 10 · Detailed Analysis of the Six-Layer Cycle Radar
• Chapter 11 · In-Depth Financial Analysis
• Chapter 12 · Arizona/Overseas Fab Economics
• Chapter 13 · CoWoS Packaging Economics
• Chapter 14 · SOTP and OVM Valuation
• Chapter 15 · DCF Valuation Model

Part D · Strategic Depth

• Chapter 16 · Polymarket Probability Matrix
• Chapter 17 · AI Impact Matrix
• Chapter 18 · Geopolitical Risk Quantification: Three Scenarios
• Chapter 19 · Technology Roadmap and Substitution Threats
• Chapter 20 · Four Major Stress Tests
• Chapter 21 · Five-Engine Synergy Analysis
• Chapter 22 · Smart Money Tracking and Signal Interpretation
• Chapter 23 · PPDA Probability-Price Divergence Analysis

Part E · Bear Case Challenges

• Chapter 24 · Bear Case Analysis (Part 1): Geopolitics/AI Bubble/Competition/Valuation
• Chapter 25 · Bear Case Analysis (Part 2): Cycle/Concentration/CapEx/Policy
• Chapter 26 · Risk Correlation Matrix and Disproof Challenges

Part F · Decision Framework

• Chapter 27 · 12-Month Investment Calendar
• Chapter 28 · CQ Closed Loop: Eight Core Questions: Final Answers
• Chapter 29 · Overall Rating and Investment Thesis

Core Questions (CQ) Checklist

CQ1：AI Supercycle Sustainability (Weight: S-Tier)

Core Question：Is AI chip demand structural or cyclical—When will TSMC's AI supercycle peak?

Final Assessment：Structural growth, 85% confidence. HPC CapEx of $635-665B (2026E) and FY2026 +30% guidance continue to validate this.

Key Uncertainty：Whether there will be a cyclical decline in CapEx in 2027-2028

CQ2：Capital Efficiency (Weight: A-Tier)

Core Question：Can $38-42B in CapEx generate reasonable returns—Is TSMC's capital efficiency deteriorating?

Final Assessment：Short-term pressure is manageable, 70% confidence. FCF of $16.1B (FY2025) vs. historical high CapEx, extended payback period for new fabs.

Key Uncertainty：Whether overseas fab ROI meets expectations

CQ3：Pricing Power Sustainability (Weight: A-Tier)

Core Question：Is the 4-year price increase plan sustainable—Does monopolistic pricing power have a ceiling?

Final Assessment：Highly sustainable, 85% confidence. Advanced nodes ~90% share, no alternative options for customers.

Key Uncertainty：Whether price increases accelerate Intel/Samsung's catch-up

CQ4：N2 Mass Production Risk (Weight: B-Tier)

Core Question：Will N2 mass production replicate N3's success—Hidden risks of GAA architecture transition?

Final Assessment：High probability of success, 80% confidence. Yield rate of 70-80% is much better than N3's initial 55%.

Key Uncertainty：Unknown challenges of GAA architecture mass production scaling

CQ5：Gross Margin Sustainability (Weight: A-Tier)

Core Question：Is a gross margin of 60%+ the new normal or a cyclical peak?

Final Assessment：Long-term new normal of 55-58%, 75% confidence. N2 ramp and overseas fabs each dilute 2-3%, partially offset by price increases + portfolio optimization.

Key Uncertainty：Cost control for Arizona/Japan fabs

CQ6：Geopolitical Risk Pricing (Weight: A-Tier)

Core Question：Is geopolitical risk a discount or a premium—How much Taiwan Strait risk has the market priced in?

Final Assessment：Over-discounted, 70% confidence. P/E of 25.7x vs. industry average of 42.7x, $165B US investment is mitigating the discount.

Key Uncertainty：Whether military confrontation in the Taiwan Strait escalates

CQ7：Valuation Ceiling (Weight: A-Tier)

Core Question：Is 26x forward P/E a historical extreme or the new normal?

Final Assessment：Reasonably high but not a bubble, 65% confidence. Monopolistic infrastructure should command a premium.

Key Uncertainty：Changes in interest rate environment and sentiment inflection points

CQ8：Customer Concentration (Weight: B-Tier)

Core Question：NVIDIA surpasses Apple to become the largest customer—Is the change in customer structure good or bad?

Final Assessment：Short-term positive, long-term requires monitoring, 75% confidence. NVIDIA's share of ~22% boosts AI revenue but increases dependency.

Key Uncertainty：Whether customers with self-developed chips (e.g., Google/Amazon) can effectively diversify the customer base

Chapter 1: Executive Summary

A comprehensive positioning and ecosystem analysis of TSMC was conducted across 10 modules, covering company panorama, industry chain mapping, AI supercycle positioning, six-layer cycle radar, technology node competitiveness, prediction market probability matrix, AI impact matrix, three geopolitical risk scenarios, customer concentration, and market attention radar updates. Here are the key findings:

I. Positioning Reshaped: From Foundry to AI Computing Chokepoint. TSMC has evolved from a traditional wafer foundry (Foundry 1.0-2.0) into the core hub of global AI computing infrastructure (Foundry 3.0). Approximately 90% of global advanced node (<=7nm) capacity is concentrated here, with NVIDIA H100/B100/GB200, Apple A/M series, and AMD EPYC/MI series all exclusively manufactured by TSMC. This "qualitative shift to indispensability" has transformed TSMC from a "service provider" to a "price setter."

II. The AI supercycle is in a transition phase from Stage 2 to Stage 3. HPC CapEx is projected to reach $602B in 2026E (+36% YoY), with inference demand surging from 1/3 to 2/3 of total AI computing power. TSMC benefits from both training (NVIDIA GPU) and inference (Google TPU/Amazon Trainium/in-house ASICs) demands. HPC revenue share soared from 43% in FY2023 to 58% in FY2025, with AI accelerator CAGR of 54-56% (management guidance). Five strong pieces of evidence for cycle sustainability: N2 fully booked for the entire year, CoWoS oversubscribed until end of 2026, inference chip market growing from $20B to $50B+, NVIDIA locking in 60%+ advanced packaging capacity, and Jensen Huang calling for a doubling of capacity.

III. The Six-Layer Cycle Radar indicates a transition from "Expansion" to "Peak" phase. The CapEx and earnings layers are in strong expansion (strongest signal), the pricing layer is at an expansion peak (5 consecutive years of price increases), the inventory layer is healthy and tight (AI undersupply + non-AI balance), the macro layer is in the mid-to-late stage of expansion (CAPE 40.58 + Buffett Indicator 224% suggests overheating), and the sentiment layer is optimistic but mixed (analysts' consensus Strong Buy, but Put/Call ratio of 1.72 suggests institutional hedging). Overall assessment: Fundamentals remain strong, but downside risks are accumulating.

IV. Technology moat is solid, but competition will intensify in 2027-2028. N2 node yield rate is 70-80% (better than N3 at the same stage), with two fabs' capacity of 100K wpm fully booked. vs. Samsung SF2P (yield just reached 70%, capacity 21-50K wpm) with an effective node advantage of 12-18 months; vs. Intel 18A (yield 55-65%, external customers only Microsoft) with an even greater advantage. However, Intel's PowerVia backside power delivery technology is 6-12 months ahead, and Samsung SF2P's yield rate breaking through to 70% is a signal worth noting.

V. Geopolitical risks are slightly over-priced by the market. Three-scenario analysis: Gray Zone 55-65% (impact -5% to -15%), Blockade 8-12% (impact -30% to -50%), Full-scale Conflict 3-5% (impact -80% to -90%). Probability-weighted loss is approximately -11.4%, while the current P/E ratio implies a discount of 14-21%, with an excess discount of 3-10%. Overseas capacity expansion roadmap: ~10% by 2026 → ~15% by 2027 → ~20% by 2028 ("Survival Line"), which can narrow the discount by 1.5-2.5% annually.

VI. NVIDIA accounting for 22% of revenue is in the "sweet spot". Two-way dependency analysis shows NVIDIA's reliance on TSM (100% manufacturing) is significantly greater than the inverse dependency (22% revenue). In-house chip customers (Google/Amazon/Microsoft/OpenAI) are estimated to collectively contribute $8-17B (5-11%) by 2026E, forming a natural hedge. HHI is approximately 1,060 (moderate concentration), expected to decline after FY2026 as customer diversification progresses.

VII. Prediction market signals lean optimistic. PMSI Composite Index 76.8/100 (v26.0 precise probability formula). Three major pricing divergences all point to undervaluation: excessive geopolitical discount (P/E 23x vs. industry 41.8x), AI premium not fully reflected (AI accelerators account for only 17-19% but broad AI exposure covers 61% of revenue), and tariff benefits not yet fully realized. The AI-adjusted P/E of 23.3x is nearly identical to the market's priced P/E of 23.1x, indicating that the geopolitical discount almost entirely offsets the AI premium. Company-level L×S positioning is L3×S3 (revenue-weighted), corresponding to a 20-50% premium range.

VIII. Key Risk: CEO's "Catastrophe" Warning. C.C. Wei admitted a sense of apprehension regarding the $52-56B CapEx, implying limited demand visibility for 2028-2029. A 40% probability of an AI bubble (Polymarket) is the biggest overhanging risk, but its transmission to TSM is weaker than to NVIDIA (AI accelerators account for only 17-19% vs. NVIDIA's 100%).

Summary. Fundamentals are extremely strong (gross margin expanding to 63-65%, N2 sold out, CoWoS monopoly), but valuation has largely priced in optimistic expectations, leading to a thin margin of safety (analyst target $392-410 vs. current $355, implying only +10-15% upside). Key modeling areas: CapEx return on investment, gross margin sustainability, DCF/SOTP valuation cross-validation.

Chapter 2: Market Attention Radar and Non-Consensus Perspectives

Attention Ranking

Non-Consensus Perspective Identification

Chapter 3: Company Profile Panorama

Core Positioning: From "Foundry" to "Central Hub of Computing Infrastructure"

Taiwan Semiconductor Manufacturing Company (TSMC, NYSE: TSM) is not an ordinary semiconductor foundry. It is the physical layer infrastructure of the global digital economy – if cloud computing is the "water and electricity of the digital world," then TSMC is the "sole factory manufacturing the pipes and cables."

Key Identity Evolution:

The core characteristic of the current phase (3.0) is a qualitative change in indispensability. In phases 1.0 and 2.0, customers chose TSMC because of "optimal cost-effectiveness"; in phase 3.0, customers choose TSMC because there is "no alternative" – approximately 90% of global advanced node (<=7nm) capacity is concentrated in TSMC's hands. NVIDIA's H100/B100/GB200 GPUs, Apple's A/M series processors, and AMD's EPYC/MI series are all, and can only be, manufactured by TSMC.

Business Model Deconstruction: Four Key Business Lines

TSMC's revenue is derived from four closely coupled business lines:

Pricing Model: Billed by the number of wafers delivered, with the unit price determined by the process node. The unit price for a 3nm wafer is approximately $20,000, 5nm is about $17,000, 7nm is about $10,000, and 28nm is about $3,000. This means that with each generation of process iteration, TSMC's revenue per wafer almost doubles—this is the core driver for the expansion of profit margins from 54% to 63%.

Customer Lock-in Mechanism: TSMC's moat is not only its technological leadership but also its ecosystem lock-in. Each customer taping out at TSMC requires:

1. Process Design Kit (PDK): Based on TSMC's specific process design rules, customer chip design is deeply coupled with the PDK. Switching foundries = redesigning the chip (12-18 months + hundreds of millions of USD)
2. IP Ecosystem: ARM cores, and Synopsys/Cadence EDA toolchains are all optimized for TSMC's process, forming a three-way lock-in.
3. Yield Learning Curve: Yield data accumulated by early customers (e.g., Apple) on new nodes constitutes a competitive barrier—newcomers require an additional 6-12 months to achieve comparable yields.
4. NRE (Non-Recurring Engineering): 3nm NRE is approximately $300-500M; once invested, it is non-recoverable.

Revenue Structure Profile

By End Platform:

By Process Node:

By Region: North America > 65% (NVIDIA +Apple +AMD + Qualcomm + Broadcom concentrated here), China ~10%, Japan ~5%, Europe ~5%, Others ~15%.

Core Competency Triangle

These three elements form a self-reinforcing flywheel: Technological leadership -> Attracting the best customers (Apple/NVIDIA) -> Customers contribute massive wafer volumes -> Economies of scale reduce unit costs & accelerate yield learning -> More R&D investment -> Continued leadership in the next generation of technology. The dilemma for competitors (Samsung Foundry, Intel Foundry) is that they need to catch up simultaneously across all three dimensions, while TSMC is accelerating in all three dimensions at the same time.

Chapter 4: Comprehensive Supply Chain Mapping

Full Supply Chain Flow Diagram

Upstream: Equipment and Materials Supply Chain

TSMC's upstream supply chain exhibits an "hourglass" structure—a few key equipment manufacturers control the lifeline of chip manufacturing.

EUV Lithography Machines -- ASML (Sole Supplier):

ASML is the world's sole company capable of producing EUV (Extreme Ultraviolet) lithography machines. All of TSMC's advanced nodes below N7 rely on EUV, with each ASML EUV lithography machine (NXE:3800E) costing approximately $200M, and the next-generation High-NA EUV (EXE:5000 series) priced at about $350M. TSMC is ASML's largest customer, contributing about 30% of its revenue.

Key Dependence Paradox: TSMC has an absolute reliance on ASML (no EUV means no advanced nodes), but ASML also has a high dependence on TSMC (TSMC orders account for 30%). This "mutual hostage" situation creates a unique strategic equilibrium—ASML will not significantly raise prices for TSMC (fearing TSMC's delayed orders would impact its own capacity planning), and TSMC will not push for lower prices (fearing ASML would reduce capacity allocation).

Etch/Deposition/Inspection -- US-Japan Big Three:

Silicon Wafers and Chemicals: Shin-Etsu Chemical and SUMCO collectively control approximately 60% of the global silicon wafer supply. Suppliers of specialty chemicals (photoresists/CMP slurries/etching solutions) include JSR, TOK, Entegris, etc. While the supply chains for these materials are fragmented, suppliers for specific categories (such as EUV photoresists) are extremely limited.

Midstream: TSMC's Three-Tier Manufacturing Capabilities

TSMC has evolved from a pure "front-end foundry" into an integrated platform covering front-end manufacturing + back-end packaging + mask manufacturing:

Front-End Manufacturing (Logic Foundry): Core business, from wafer start to process completion. Current mass production nodes cover N2 (2nm)/N3 (3nm)/N5 (5nm)/N7 (7nm) as well as mature nodes (16nm/28nm/40nm/65nm, etc.). A16 (1.6nm) mass production will be added in 2026.

Advanced Packaging (CoWoS/InFO/SoIC): This represents TSMC's most critical capacity bottleneck from 2024-2026, and also the physical limit of the AI computing power supply chain.

• CoWoS(Chip-on-Wafer-on-Substrate): Used for stacking GPU dies with HBM (High Bandwidth Memory) for packaging, and all NVIDIA AI GPUs (H100/B100/GB200) utilize CoWoS. Monthly capacity is expected to expand from approximately 35K wafers by the end of 2024 to a target of 130K wafers by the end of 2026 (a nearly 4x increase in capacity).
• InFO(Integrated Fan-Out): Used for Apple A/M series processors, with lower cost than CoWoS but sufficient performance for mobile applications.
• SoIC(System-on-Integrated-Chips): 3D stacking technology, representing the direction for next-generation heterogeneous integration, and is currently in early-stage mass production.

Mask Manufacturing: TSMC possesses the world's most advanced EUV mask manufacturing capabilities, a capability that is highly internalized and difficult for external competitors to replicate.

Downstream: Design Companies and End Markets

TSMC's top five customers collectively contribute approximately 62% of its revenue:

The transmission chain of the downstream end-market is: Design Companies (NVIDIA/Apple) -> System Manufacturers (Dell/HP/SuperMicro) -> End Users (Data Centers/Mobile Phones/Automotive). TSMC does not directly face the end-market, but its capacity allocation decisions essentially determine "who gets AI chips first".

Supply Chain Power Analysis

TSMC's Bargaining Power with Upstream Suppliers -- Medium-Strong:

TSMC is the largest or one of the top three customers for almost all semiconductor equipment manufacturers, which grants it significant procurement bargaining power. However, ASML's monopolistic position in EUV creates a counterbalance – TSMC cannot "threaten to switch suppliers" to pressure ASML on prices. The net effect is: TSMC can secure priority in equipment delivery schedules (ASML delivers to TSMC first), but its bargaining room on equipment unit prices is limited.

TSMC's Bargaining Power with Downstream Customers -- Extremely Strong and Still Increasing:

The irreplaceable nature of advanced nodes grants TSMC nearly absolute pricing power. Key evidence:

1. 4-Year Price Hike Plan: TSMC announced in 2024 a gradual price increase from 2025-2028, with 3nm prices rising by 5-8% and CoWoS prices by 10-20%
2. Capacity Allocation Rights: CoWoS capacity is sold out, and TSMC determines how much packaging capacity NVIDIA, AMD, and Broadcom each receive – this is essentially the "physical power to allocate AI compute".
3. Customers Cannot Resist: If NVIDIA wanted to switch foundries to Samsung or Intel, it would require a re-tapeout + yield ramp-up of at least 18-24 months, and the AI race window does not allow for such a wait.

However, long-term balancing factors exist: NVIDIA has allocated the I/O die (approximately 25% of production) for its Feynman architecture to Intel Foundry, and Apple is also exploring Intel 18A. While this "multi-sourcing" strategy has limited short-term impact, it sends an important signal: major customers will not forever accept the absolute control of a single foundry. (-> CQ8 customer structure changes)

Key Supply Chain Bottlenecks (2026):

Chapter 5: Precisely Positioning the AI Supercycle

5.1 Four-Stage Model of the AI Supercycle

AI hardware investment is not a singular wave but a supercycle with distinct stage characteristics. Based on hyperscaler CapEx trajectories, evolving chip type demand, and application deployment pace, it can be divided into four overlapping but progressive stages:

Stage 1: Infrastructure Buildout (2023-2024)

• Milestones: Large-scale GPU procurement, data center construction, power expansion
• Primary Beneficiaries: NVIDIA A100/H100, TSMC N5/N4 nodes
• CapEx Driver: Hyperscaler total expenditure went from $477B in 2022 to $256B in 2024 (Top 5 for a single year)
• Characteristics: "Buy GPUs if you have money" panic buying, severe supply shortage

Stage 2: Training Expansion (2024-2025)

• Milestones: Large model parameter race (GPT-5, Gemini Ultra, Llama 4), ten-thousand-card cluster buildout
• Primary Beneficiaries: NVIDIA H200/B100/B200, explosion in CoWoS advanced packaging demand
• CapEx Driver: Top 5 hyperscaler CapEx reached $443B in 2025 (+73% YoY)
• Characteristics: Exponential growth in training compute demand, CoWoS becomes the tightest bottleneck

Stage 3: Inference Deployment (2025-2027) <-- TSM's current core beneficiary period

• Milestones: Enterprise AI Agent deployment, high-volume edge inference chip production, inference's share of compute rising from 1/3 to 2/3
• Primary Beneficiaries: NVIDIA Blackwell/Rubin inference optimization, AMD MI400, Custom ASICs (Broadcom/Marvell)
• CapEx Driver: Top 5 hyperscaler CapEx is projected to reach $602B in 2026 (+36% YoY), approaching $700B including operating expenses
• Characteristics: Inference workloads are expected to account for approximately 2/3 of all AI compute in 2026, doubling from 1/3 in 2023

Stage 4: Application Monetization (2027+)

• Milestones: Maturation of AI-native business models, ROI validation, potential slowdown in CapEx growth
• Risk: Hyperscalers find AI investment returns fall short of expectations, leading to CapEx reductions
• Goldman Sachs Forecast: Cumulative hyperscaler CapEx for the three years 2025-2027 projected at $1.15 trillion, doubling the previous three years

5.2 TSM's Precise Position in the Cycle

TSM's uniqueness lies in: benefiting simultaneously from the tail end of Stage 2 and the full unfolding of Stage 3. This stems from its "chokepoint" position in the supply chain.

Training Side (Continuation of Stage 2):

• NVIDIA Rubin architecture (R100) is expected to enter mass production by late 2026, still requiring TSMC N3/N2 nodes + CoWoS-L packaging
• NVIDIA has already locked in 60%+ of TSMC's advanced packaging capacity for 2026
• Large model training has not decreased due to the rise of inference – GPT-5 class models are still expanding

Inference Side (Main Driver of Stage 3):

• The inference chip market is projected to exceed $50 billion in 2026, a 150% increase from over $20 billion in 2025
• AI PC market share to reach 55% in 2026 (only 31% in 2025)
• 40% of enterprise applications will incorporate AI Agents (only <5% in 2025)
• Qualcomm, MediaTek, and other inference chip designers are all TSMC N3/N2 customers

Quantifying TSM's "Dual Benefit":

• HPC Platform Revenue Share: 43% in 2023 -> 51% in 2024 -> 58% in 2025
• Advanced Process (<=7nm) Revenue Share: 58% in 2023 -> 69% in 2024 -> 74% in 2025
• N2 Capacity fully booked for 2026 across both fabs, targeting 100K wafers per month

5.3 Five Key Pieces of Evidence for Cycle Durability

5.4 Cycle Peak Risk: CEO's "Big Disaster" Warning

TSMC CEO C.C. Wei's candid statement is worth pondering: "I'm also very nervous about it... If we don't do it carefully, that'd be a big disaster for TSMC"

Three-Layer Analysis of Peak Risk:

1. CapEx Mismatch Risk: Capacity built with $52-56B in 2026 capital expenditures will only be fully released by 2028-2029. If AI demand slows down in 2027, TSMC will face overcapacity.

2. FCF Pressure: FY2025 CapEx has already reached NT$1,093.5B, further increasing to $38-42B (~NT$1,216-1,344B) in 2026. Free cash flow is under pressure due to massive CapEx.

3. Weak Non-AI Demand: Smartphone platform revenue share decreased from 33% in 2023 to 29% in 2025, while IoT and automotive each account for only 5%. Demand outside of AI is largely stable, indicating TSM's increasing reliance on AI as a sole driver.

4. Customer Concentration Risk: NVIDIA has locked in 60%+ of advanced packaging capacity. If NVIDIA itself experiences a demand slowdown (custom ASIC alternatives, inference optimization reducing GPU demand), TSM will directly bear the impact.

5.5 Probability Distribution Assessment

Key Observation: 55% continued strong growth + 30% delayed peak = 85% probability that TSM's revenue will remain strong in the next 12-18 months. However, the thermometer reading of +0.795 (overheated) reminds us that the market has partially priced in the optimistic scenario.

Chapter 6: In-Depth Analysis of Technology Node Competitiveness

6.1 Three-Way Comparison Matrix: TSM N2 vs Samsung SF2P vs Intel 18A

6.2 Quantifying TSM's Technology Moat

Time-to-Parity:

• vs Samsung: TSMC N2 HVM starts in 2025Q4, Samsung SF2P targets 2026Q2. The superficial gap is only about 6 months, but the yield rate difference is more critical—TSMC reaches 70-80% yield at HVM, while Samsung just reached 70% and only for test chips. Based on historical experience, it usually takes Samsung 6-12 months to move from 70% test yield to stable volume production levels (>80%), hence the actual effective time-to-parity is about 12-18 months

• vs Intel: Intel 18A HVM starts in 2026Q1, trailing TSMC by only about 3 months in terms of timing. However, Intel's 65-75% yield rate is still lower than TSMC's 70-80%, and Intel has almost no external customers (foundry business)—Microsoft is the only confirmed customer, with Apple/NVIDIA only indicating interest for 2028. Intel's challenge is not technology (where PowerVia leads) but customer ecosystem and capacity scale

Capacity Gap:

Economic Implications of Yield Rate Gap:

Assuming N2 wafer cost of $30,000/wafer, chip area 100mm^2:

• TSMC 80% yield: Effective chip cost ~$37,500/wafer equivalent of good dies
• Samsung 70% yield: Effective chip cost ~$42,857/wafer equivalent of good dies
• Intel 65% yield: Effective chip cost ~$46,154/wafer equivalent of good dies

TSM's effective cost advantage per wafer is approximately 10-19%, which directly translates into an economic rationale for customers to choose TSMC.

6.3 Competitive Catch-up Timeline

Key Assessment: When can Samsung and Intel reach TSMC's current N2 level?

• Samsung: For SF2P to reach TSMC N2's current mass production maturity (80%+ yield + 100K wpm capacity), the optimistic estimate is 2027H1, and the conservative estimate is 2027H2-2028. By then, TSMC will already be at the N2P/A16 or even N1.4 nodes. Samsung is always chasing the previous generation.

• Intel: Intel's 18A PowerVia technology is indeed leading, but customer acquisition for its foundry business is the biggest bottleneck. Even if 18A yield reaches 80% in 2027, without major customer orders from Apple/NVIDIA, capacity utilization cannot sustain economic viability. Intel's foundry turnaround is more likely in 2028 (if Apple orders materialize).

6.4 Backside Power Delivery (BSPDN) Competition: PowerVia vs SPR

BSPDN (Backside Power Delivery) is considered the next major architectural innovation after 2nm. It moves power lines from the front to the back of the chip, freeing up routing space on the front and delivering dual benefits in performance and power consumption.

Investment Implications of BSPDN Competition: Intel indeed has a 6-12 month lead in BSPDN, which is one of its few technological highlights. However, technological leadership does not equate to commercial success—Intel 18A's customers are still primarily for internal use (Clearwater Forest CPU), with very few external foundry orders. While TSMC's SPR is slightly later, once it achieves mass production at the A16 node, the natural migration of customers like NVIDIA will quickly give it a scale advantage.

6.5 Four Years of Price Hikes and the Dynamic Game of Competitive Catch-up

TSMC has continuously raised prices for advanced nodes for 4 years (2022-2025, annual average 5-15%), and will continue to raise prices by 3-10% in 2026. This creates a delicate competitive dynamic:

Self-limiting Mechanism of Price Increases:

• Each price increase is narrowing the price gap between TSMC and Samsung/Intel
• If TSMC N2 wafers are $30,000+ vs Samsung SF2P possibly $22,000-25,000, a 20-35% price difference might compel price-sensitive customers (e.g., mid-range smartphone SoCs) to switch to Samsung
• Qualcomm and AMD are already in talks with Samsung regarding SF2P

But pricing power itself proves the moat:

• 5 consecutive years of price increases without customer attrition (advanced nodes) indicates extremely high switching costs
• Yield gap (10-15%) offsets the price gap – even factoring in yield, TSMC's effective cost may still be lower than Samsung's
• Monopoly in advanced packaging (CoWoS) is the "second lock" to retain customers

Chapter 7: Customer Concentration Risk Analysis

Evolution of Customer Concentration: From the Apple Era to the NVIDIA Era

In January 2026, NVIDIA CEO Jensen Huang personally confirmed: NVIDIA has surpassed Apple to become TSMC's largest customer. This "shift" is not only a change in revenue ranking but also marks a paradigm shift in the semiconductor industry from "mobile computing" to "AI computing."

Historical Evolution of Customer Structure:

Key Observation: Top5 concentration increased from 55% in FY2019 to 62% in FY2025, primarily driven by NVIDIA's share rising from <5% to 22%. Concurrently, Apple's share actually decreased by approximately 5 percentage points (from ~25% to ~18%).

In-depth Analysis of NVIDIA Dependency: Who Needs Whom More?

This is the core debate of CQ8. Superficially, TSM's revenue dependence on NVIDIA (22%) appears to be a risk. However, a two-way dependency analysis reveals a more complex picture:

TSM's Dependency on NVIDIA:

NVIDIA's Dependency on TSM:

Conclusion: NVIDIA's dependency on TSM is significantly greater than TSM's dependency on NVIDIA. This asymmetrical relationship grants TSM a structural advantage in pricing negotiations – NVIDIA's AI GPU gross margin is >70%, so even if TSM raises prices by 10%, NVIDIA "doesn't care" because there are no alternatives.

Feasibility Assessment of NVIDIA Replacing TSM

Samsung: Led mass production of 3nm GAA in 2022, but yield issues resulted in almost no major customer adoption. SF2 (2nm) is expected to begin pilot production in 2026H2, but market confidence is low. TrendForce reported that Samsung might become NVIDIA's "second supplier," but only for mature nodes or specific product lines.

Intel: NVIDIA purchased a $4.86B stake in Intel, interpreted as a strategic signal for supply chain diversification. Intel 18A is benchmarked against TSM N2 on the technology roadmap, but (a) Intel Foundry has yet to prove its large-scale foundry capabilities, and (b) Intel's own chips receive priority for capacity. The earliest significant capacity diversion is likely in 2027-2028.

Bottom line: In the 2026-2028 window, NVIDIA has virtually **no viable alternatives**. This means TSM's 22% revenue reliance on NVIDIA has extremely high stability and predictability in the short term.

Customer Diversification Trend: In-house Chip Customers Are Rising

This is an **underestimated positive factor** in the market. Even with NVIDIA's high proportion, the customer base for in-house chips (Custom Silicon) is rapidly expanding, naturally diversifying TSM's reliance on any single customer:

Total Estimated 2026E Revenue Contribution from In-house Chip Customers: $8-17B, accounting for 5-11% of TSM's FY2026E revenue

Significance of the Trend: These customers were almost non-existent in TSM's revenue structure three years ago. By 2028, in-house chip customers combined could account for 10-15% of TSM's revenue, becoming a "third pole" second only to NVIDIA and Apple. More importantly, the demand from these customers is **partially substitutable and partially complementary** to NVIDIA's GPU demand — they are primarily used for inference rather than training, forming a more balanced AI chip demand structure.

Dual-Nature Analysis Framework

Changes in customer concentration cannot be simply categorized as "good" or "bad" — it is a structural shift with a dual nature:

Stress Test: NVIDIA Revenue Decline 30% Scenario

Assumption: NVIDIA's orders to TSM decrease by 30% due to an AI CapEx cycle downturn / intensified competition / export controls

Net Impact: TSM revenue declines by 4-5%, gross margin by 1-2%, but **does not constitute an existential threat**. More importantly, the rapid growth of in-house chip customers (Google/Amazon/Microsoft/OpenAI) provides a **natural hedge** — even if NVIDIA's demand declines, the total demand for AI chips (training + inference) continues to grow, with market share simply shifting from NVIDIA GPUs to in-house ASICs.

HHI Index and Concentration Monitoring

The Herfindahl-Hirschman Index (HHI) is used to quantify customer concentration risk:

Trend: After peaking at ~1,060 in FY2025, the HHI is expected to decline as in-house chip design clients grow. An HHI between 1,000-1,500 is considered "moderately concentrated" (not highly concentrated), indicating controllable risk.

Chapter 8: Moat Quantification and Competitive Matrix

8.1 Moat Overview

TSM's moat system consists of five mutually reinforcing layers of barriers, forming the deepest competitive defense in the semiconductor industry. Each moat category is quantified and analyzed below, with scores supported by at least three hard data points.

8.2 Moat A: Technological Leadership (Technology Lead) — Score 9.5/10

8.2.1 Process Node Gap Quantification

3nm Node Yield Comparison:

Samsung's 3nm yield is "stuck at 50%", significantly lagging TSM's 90%+. This 40 percentage point yield gap means Samsung's effective output per wafer is only about 56% of TSM's, directly leading to nearly double the unit cost.

Several companies that initially explored Samsung's advanced nodes shifted to TSM after trial production failures, including critical design orders from Qualcomm and NVIDIA.

2nm Node Yield Comparison (Verification):

TSM's 2nm yield is approximately 65% and continuously improving, while Samsung's 2nm (SF2) is around 40%. TSM's yield advantage is "making it hard for Samsung to win clients".

Samsung's 2nm yield reached 55-60%, but this is under controlled conditions; actual mass production yields are expected to be lower.

Intel 18A yield has just crossed the 60% threshold, but "yields only set to reach industry standard levels in 2027", with an average improvement rate of about 7%/month.

8.2.2 Competitive Catch-Up Timeline

Catch-up Time Assessment:

• Samsung will require 3-5 years to catch up to TSM's 3nm lead (50% vs 90%). Historically, Samsung's catch-up cycles for 14nm/10nm/7nm were 3-4 years, but the exponentially increasing complexity of advanced nodes makes catching up more challenging.
• Intel 18A will require approximately 12-18 months to go from 60% yield to industry standard (>80%), meaning by mid-2027. However, Intel lacks external customer validation experience, so its actual foundry competitiveness will require an additional 1-2 years.
• Conclusion: Samsung/Intel will require 3-5 years to catch up to TSM's current level, and TSM will continue to advance during this period (A16/A14), meaning the actual process gap may never be fully eliminated.

8.2.3 Advanced Packaging Technology Barriers

TSM CoWoS capacity expands from 35K wpm by end of 2024 to 75K wpm by end of 2025, targeting 130K wpm by end of 2026 — nearly 4x expansion in three years.

NVIDIA has secured **over 60%** of TSM's 2026 CoWoS capacity, with key customers collectively securing **>85%** of capacity, while second-tier manufacturers compete for the remaining <15%.

This monopoly in packaging capacity constitutes a critical extension of its technological moat: Even if competitors catch up in wafer manufacturing, a lack of advanced packaging capabilities prevents them from meeting the full demands of AI chip customers. Intel's EMIB/Foveros are being explored as alternatives, but their scale is far smaller than TSM's.

Technological Leadership Moat Data Summary:

• 3nm Yield Gap: TSM >90% vs Samsung ~50% = 40pp advantage
• 2nm Mass Production Time Gap: TSM leads Samsung/Intel by approximately 6-12 months
• CoWoS Capacity: Global advanced packaging market share **>80%**
• N2 First-Year Tape-out Volume: 2x that of N5 in the same period

8.3 Moat B: Switching Cost — Score 9.0/10

8.3.1 Design Investment Lock-in

Chip design costs grow exponentially as nodes shrink, creating a significant switching barrier:

The full-flow design cost for a 3nm chip is approximately $590M, and for 2nm, it is expected to exceed $800M. Once these investments are made for a specific foundry's PDK (Process Design Kit), switching to another foundry means redesigning the entire chip, resulting in significant cost and time losses.

The unit price for a 2nm wafer is expected to exceed $30,000/wafer, an increase of over 50% compared to 3nm's $20,000-$25,000. This price increase further raises the demands for foundry yield and reliability, strengthening TSM's lock-in effect.

8.3.2 IP Library and PDK Ecosystem Lock-in

IP Library Depth:

• Synopsys provides certified EDA flows for TSM A16 and N2P, covering a complete set of IPs including 1.6T Ethernet, PCIe 7.0, UCIe, HBM4, USB4, DDR5, LPDDR6.
• TSM's Open Innovation Platform gathers thousands of verified IP blocks, covering complete design requirements from logic libraries to high-speed interfaces.
• Samsung and Intel's IP library scale is approximately 30-50% of TSM's, with an even greater gap in the availability and verification maturity of advanced node IPs.

8.3.3 Historical Switching Failure Cases

• Apple → Samsung → TSMC (2016): During the A9 chip era, Apple simultaneously used Samsung 14nm and TSM 16nm, finding the Samsung version had higher power consumption and lower yield. Subsequently, Apple fully transitioned to TSM and has continued to do so (A17 Pro/M4 both use N3).
• Qualcomm Multiple Attempts with Samsung: Qualcomm used Samsung 4nm for its Snapdragon 8 Gen 1, which received market criticism due to power consumption and heating issues. Starting with 8 Gen 2, Qualcomm switched back to TSM N4.
• NVIDIA Exclusively TSM: From Ampere to Hopper to Blackwell, NVIDIA has never used a non-TSM foundry. Even when facing CoWoS capacity bottlenecks, it chose to wait rather than switch.

Switching Cost Moat Data Summary:

• 3nm Chip Design Cost: $590M — Switching = Re-investment
• Design Verification Cycle: 18-36 months — Switching delays are unacceptable
• Failure Cases: Apple/Qualcomm returned to TSM from Samsung — Extremely high switching failure rate
• PDK/IP Lock-in Depth: Thousands of verified IPs vs Samsung/Intel's 30-50% coverage

8.4 Moat C: Scale Economy — Score 9.0/10

8.4.1 CapEx Investment Barrier

TSM's 2026 CapEx guidance is **$52-56B**, an increase of approximately 35% from 2025. This figure exceeds the combined 2025 CapEx of Intel and Samsung (Intel ~$18B + Samsung Semiconductor ~$20B = ~$38B).

TSM CapEx Allocation: ~70% for advanced logic process equipment and new fab construction, 10-20% for advanced packaging, ~10% for specialty technologies.

TSM's absolute scale of investment enables it to simultaneously advance multiple generations of process R&D (N2/A16/A14) + global capacity expansion (Arizona/Kumamoto/Germany), whereas competitors, under financial constraints, can only invest selectively.

8.4.2 R&D Efficiency Advantage

TSM invests only 7% of its revenue in R&D, yet achieves the industry's highest yield and most advanced nodes. Intel invests 31% of its revenue (absolute amount $16.5B) but is still catching up. This reflects TSM's R&D efficiency is 6-7 times that of Intel (measured by yield/revenue investment).

TSM's R&D efficiency advantage stems from:

1. Accumulated Learning Curve: 30+ years of pure-play foundry experience, with knowledge accumulated from each node directly applied to the next generation
2. Customer Diversity: Serving the diverse needs of hundreds of customers accelerates process optimization
3. Production Scale: Larger mass production scale provides more data points for yield optimization

8.4.3 Capacity Scale and Utilization

TSM's advanced nodes (≤7nm) account for ~70% of revenue, with N3 at 24%, N5 at 32%, and N7 at 14%. Gross margin 58.62% (FY2025) → reaching 62.3% in Q4 2025 → Q1 2026 guidance 63-65%.

TSM's net profit margin of 45.1% (FY2025) vs. Intel's net profit margin of -0.5% vs. Samsung's overall OPM of 13.1%. TSM's margin advantage enables it to support its $52-56B CapEx with its own cash flow, without significant debt financing (D/E ratio of only 0.183).

Economies of Scale Moat Data Summary:

• 2026 CapEx: $52-56B — Exceeds the sum of Samsung + Intel
• R&D Efficiency: 7% of Revenue vs Intel's 31% — 6-7x difference in efficiency
• Gross Margin: 58.6-65% — Strongest capital self-sufficiency
• D/E Ratio: 0.183 — Lowest leverage level in the industry

8.5 Moat D: Network/Ecosystem — Score 8.5/10

8.5.1 Deep Integration of EDA Ecosystem

Synopsys collaborates with TSM on certified EDA flows for A16/N2P/N3C. Cadence and Siemens EDA also have deep integration with TSM.

TSM's OIP (Open Innovation Platform) Ecosystem:

• Gathers certified design flows from the three EDA giants (Synopsys, Cadence, Siemens EDA)
• AI-driven design: AI completes design in minutes (originally required engineers two days), power optimization up to 10x
• More customers use TSM → More IP/EDA verification → Easier design → Attracts more customers — Positive feedback loop

8.5.2 Advanced Packaging Ecosystem Lock-in

CoWoS capacity will reach 130K wpm by the end of 2026. NVIDIA has locked in >60% of capacity until 2027. Key customers combined have booked >85% of capacity.

In the AI era, chip performance is increasingly limited by packaging rather than process technology. TSM's dominant position in CoWoS/InFO/SoIC means that even if competitors catch up in wafer manufacturing, lacking packaging capabilities means they cannot offer a complete solution.

8.5.3 IP Partner Priority Support

• ARM, Synopsys, and other IP vendors prioritize developing and validating IP for TSM nodes
• IP availability for TSM's new nodes typically leads Samsung/Intel by 6-12 months, further solidifying customers' preference for TSM

Network Effect Moat Data Summary:

• All three EDA giants deeply certified: Synopsys/Cadence/Siemens
• CoWoS 2026 Capacity: 130K wpm, >85% booked
• IP Priority Validation Lead: TSM leads by 6-12 months
• AI Design Efficiency Improvement: 10x power optimization

8.6 Moat E: Trust & Reputation — Score 8.0/10

8.6.1 "Swiss Model" Pure-Play Foundry Trust

The pure-play foundry model established by TSM founder Morris Chang is the cornerstone of its trust advantage: TSM does not design its own chips and does not compete with customers.

Comparison with competitors' structural trust deficiencies:

Apple entrusts all its chips to TSM instead of Samsung (which was once its foundry), and one of the core reasons is that Samsung's own mobile phone business constitutes direct competition. Similarly, AMD would not easily entrust its designs to Intel for manufacturing.

8.6.2 Market Share Trend Validates Trust

TSM's foundry market share steadily climbing:

• Q1 2025: 67.6%
• Q2 2025: 70.2%
• Q3 2025: 71% (a new historical high)

Samsung's share continued to decline during the same period:

• Q1 2025: 7.7%
• Q2 2025: 7.3%
• Q3 2025: 6.8%

TSM's market share in the overall foundry market reached 71%; if only advanced nodes (≤7nm) are considered, the share approaches 90%.

8.6.3 Customer Retention and Design Start Trends

N2's first-year tape-out volume was 2x that of the same period for N5, growing to 4x N5's volume in the second year. All major AI customers (non-China) design GPUs and ASICs on the TSM platform.

Based on the top 5 customers (Apple/NVIDIA/Qualcomm/AMD/MediaTek) consistently using TSM's latest nodes for the past 5 years, the core customer retention rate is close to 100%.

TSM's trusted brand allows it to charge a 5-10% premium (price increase announced for 2026), and customers are still willing to pay because the switching risk far outweighs the price difference.

Brand Trust Moat Data Summary:

• Pure-Play Foundry Model: Does not compete with customers — Structural trust advantage
• Foundry Market Share: 71% (Q3 2025), advanced nodes ~90%
• N2 Tape-out Trend: 2-4x that of N5 at the same stage
• Top 5 Customer Retention Rate: Close to 100% (5 consecutive years)

8.7 Competitive Matrix: TSM vs Samsung vs Intel vs SMIC

8.7.1 Comprehensive Competitive Comparison Table

8.7.2 Competitive Positioning Quadrant Chart

8.7.3 In-depth Assessment of Competitors

Samsung Foundry:

• Market share decreased from ~10% in 2024 to 6.8% in Q3 2025. Foundry business continues to incur losses, aiming for profitability by 2027.
• Recently secured Tesla AI5 chip orders and Nintendo Switch 2 orders, demonstrating continued competitiveness in the mid-range market.
• Samsung has a theoretical advantage in 2nm GAA (adopting GAA earlier than TSM), but mass production yield remains a critical bottleneck. Even if SF2 achieves 60% yield, it may still lag TSM N2 by approximately 5-15 percentage points.

Intel Foundry Services (IFS):

• 18A yield has improved by 7% monthly on average, expected to reach cost-viable levels by the end of 2026. Panther Lake (18A) was showcased at CES 2026.
• Intel FY2025 OPM is approximately -0.04%, ROE is only 0.02%, indicating extremely fragile financial health. D/E of 0.408 is significantly higher than TSM's 0.183.
• Intel's foundry business faces a structural conflict of "internal priority vs. external customer trust". Under financial pressure, IFS might be spun off or scaled back.

SMIC:

• SMIC has achieved 5nm pilot production without EUV, but the yield is only about 1/3 of TSM's comparable node, and costs are 50% higher. 7nm monthly capacity is limited to "low tens of thousands" level.
• US export controls have "dramatically constrained SMIC's ability to scale up 7nm production", limiting the originally planned "hundreds of thousands of wafers/month" to "low tens of thousands".
• Without EUV equipment, SMIC will face physical limits at nodes below 5nm. The cost and yield disadvantages of multi-patterning solutions will exponentially worsen as nodes shrink.

8.8 Moat Width Score and Overall Rating

8.8.1 Five-Dimension Score Summary

8.8.2 Moat Radar Chart

8.8.3 Overall Moat Rating

Rating: Very Wide (Very Wide Moat)

TSM's moat meets the "Very Wide" standard in the following aspects:

1. Multiple Overlapping: All five types of moats have reached 8.0+ levels; erosion in any single dimension will not destabilize the overall defense.
2. Self-Reinforcing: Technological leadership → customers choose TSM → scale growth → more R&D investment → continued technological leadership — Flywheel Effect.
3. Difficult for Competitors to Catch Up: It is verified that Samsung/Intel would need 3-5 years to catch up, and TSM continues to advance.
4. Quantitative Support: Overall score of 8.98/10, placing it within Morningstar's "Very Wide" category (>8.5).

Moat Erosion Risk Factors (Requires Continuous Monitoring):

• [CQ6] Taiwan Strait Geopolitical Risk: The only exogenous variable that could instantly collapse the moat.
• [CQ8] Samsung 2nm Breakthrough: If SF2 yield reaches 80%+, it could divert customers in specific areas.
• [CQ3] Customer Diversification Pressure: Major customers are motivated to reduce TSM dependence and may support alternative suppliers in the long run.
• [CQ4] A16/A14 Execution Risk: Delays in new technologies like backside power delivery could shorten the lead time window.

8.9 Key Findings and Linkages

Core Conclusions of This Module:

1. TSM possesses the widest moat in the semiconductor industry (overall 8.98/10, Very Wide), comprising five mutually reinforcing layers of barriers.
2. Verified: Samsung/Intel would need 3-5 years to catch up to TSM's current level, and the generational gap may never be fully eliminated.
3. AI Era Widens Moat: CoWoS advanced packaging has become a new critical barrier, with TSM monopolizing >80% of the market.
4. Sole Systemic Risk: Taiwan Strait Geopolitics (CQ6) — all other competitive risks are manageable within a 3-5 year window.

Chapter 9: Six-Layer Cycle Radar

The semiconductor industry is highly cyclical. Below, we construct a six-layer cycle radar to evaluate current signals layer by layer, from macro to micro, providing multi-dimensional cross-validation for TSM's cyclical positioning.

Layer 1: Macroeconomic Layer

Macro Layer Signal: Mid-to-Late Expansion (Expansion - Late)

Robust GDP growth + declining interest rates are favorable for the technology sector, but CAPE at 40.58 and Buffett Indicator at 224% indicate that overall market valuations are highly stretched. The macroeconomic environment "supports growth but punishes high valuations"; should recession signals emerge, highly valued assets would be the first to suffer.

Layer 2: Capital Expenditure (CapEx) Layer

CapEx Layer Signal: Strong Expansion (Strong Expansion)

This is the strongest bullish signal among the six layers. Over $600B in advanced computing CapEx is not just growth, but accelerated growth. However, the deceleration in WFE growth from +9% to +7.3% suggests that the CapEx acceleration slope is moderating. Key question: Has record CapEx already been priced into the stock?

Layer 3: Pricing Layer

Pricing Layer Signal: Peak Expansion (Peak Expansion)

Five consecutive years of price increases + annual ASP growth of 15%+ represents a rare sustained period of pricing power in the semiconductor industry. The 20% CoWoS price increase reflects a genuine supply-demand gap. However, CEO C.C. Wei himself stated that "price is not the main driver of profit" (TrendForce, 2026-01-15), suggesting that the magnitude of price increases may be nearing the limit of customer tolerance.

Layer 4: Inventory Layer

Inventory Layer Signal: Healthy-Tight (Healthy-Tight)

There is a severe supply-demand imbalance in AI chips, while non-AI segments (smartphones/IoT/automotive) have returned to normal inventory levels. TSMC's own inventory days at 74 are within a healthy range (historical range 60-90 days). This structural divergence of "AI tightness + non-AI balance" differs from traditional semiconductor cycles—there is no classic "overall destocking" or "overall restocking."

Layer 5: Profitability Layer

Profitability Layer Signal: Strong Expansion (Strong Expansion)

The sustained expansion of gross margin from 54% towards 65% represents TSMC's strongest profitability cycle in its history. The drivers are clear: (1) increased proportion of advanced nodes = higher blended ASP; (2) price increases directly translate to gross profit; (3) reduced depreciation for mature nodes. However, a 65% gross margin may be approaching its theoretical ceiling (for a pure-play foundry model, requiring sustained CapEx).

Layer 6: Sentiment Layer

Sentiment Layer Signal: Bullish with Hedging (Bullish with Hedging)

Unanimous analyst bullishness + short interest of only 0.46% indicates extremely optimistic consensus. However, a Put/Call Ratio of 1.72 suggests institutional investors are hedging downside risk through options. This "bullish talk, buying puts" divergence warrants caution—when everyone is bullish, marginal sellers far outnumber marginal buyers.

Overall Scoring Matrix

Key Differences from Classic Semiconductor Cycles

Typical characteristics of a traditional semiconductor cycle (3-5 years per cycle) are: demand recovery -> price increases -> CapEx expansion -> overcapacity -> price drops -> inventory destocking. The current AI super cycle presents three key differences:

1. Structural Shift in Demand Side: AI is not an incremental increase in traditional terminal demand, but rather a brand new trillion-dollar infrastructure construction cycle. Comparable to the internet infrastructure of the 2000s and mobile internet of the 2010s, but on a larger scale and at a faster pace

2. Extreme Concentration on the Supply Side: TSMC holds over 90% market share in advanced logic manufacturing, eliminating the traditional cycle path of "multiple expansions -> overcapacity". As long as TSMC controls the pace of capacity expansion, the extent of the cyclical downturn will be limited

3. Inventory Cycle Invalidation: AI chips (GPU/ASIC) are "build-and-use" infrastructure-type procurements, eliminating the traditional "channel inventory buildup -> destocking" cycle. CoWoS supply shortages may persist until 2027

Chapter 10: Detailed Analysis of the Six-Layer Cycle Radar

10.1 Executive Summary

TSMC is currently in the mid-to-late expansion phase of the semiconductor supercycle, but structural AI demand imbues it with characteristics significantly different from traditional silicon cycles. Among the six-layer radar signals, 5 layers show an "expanding/overheating" status, with only mature node inventory/utilization being "neutral to weak". Key judgment: Advanced nodes (N3/N5/N2) will remain in short supply at least until 1H 2027, with CoWoS advanced packaging being the critical capacity bottleneck, but there is a risk of a cyclical pullback after 2028.

Overall Cycle Score: 7.8/10 (Mid-to-Late Expansion)

10.2 Layer 1: DRAM/NAND Pricing Cycle Signal

10.2.1 DRAM Spot and Contract Price Trends

The current DRAM market is experiencing the strongest price increase cycle in nearly a decade.

Key Driver: Q1 2026 memory contract prices across all categories hit a new quarterly record high. Suppliers are shifting some NAND production lines to DRAM, further exacerbating NAND supply tightness.

10.2.2 HBM3E Supply-Demand Landscape

HBM (High Bandwidth Memory) is a core component of AI accelerators, directly determining the pace of GPU shipments, and subsequently impacting TSM's advanced node and CoWoS capacity utilization.

The HBM supply-demand gap is expected to persist at least until 1H 2027. This means NVIDIA/AMD's AI accelerator shipments are constrained by HBM supply, not TSM's advanced logic foundry capacity——i.e., the bottleneck is in upstream memory, not midstream foundry.

10.2.3 NAND Flash Trends

10.2.4 Transmission Mechanism to TSM

10.3 Layer 2: Semiconductor CapEx Supercycle

10.3.1 TSM CapEx Intensity (5-Year Trend)

All CapEx and revenue data are sourced from TSM financial reports.

Key Observations:

1. CapEx Intensity Continues to Decline: From 53.5% in FY2021 to 33.4% in FY2025.
2. FY2026E Guidance: $38-42B (approx. NT$1,230-1,360B). Management confirmed FY2026E CapEx of $38-42B
3. FCF Leap: FY2025 FCF NT$1,098B, YoY +108.5%. OCF NT$2,383B vs CapEx NT$1,286B, OCF/CapEx Coverage Ratio 1.80x
4. CapEx/Depreciation Ratio: 1.49x (TTM). Indicates TSM is still actively expanding capacity; CapEx exceeding depreciation means growth in net fixed assets

10.3.2 Global Semiconductor Equipment Market

10.3.3 Global Semiconductor Industry Revenue Forecast

The semiconductor industry is projected to exceed the $1 trillion mark for the first time in 2026.

10.3.4 CapEx Return Cycle Analysis

The NT$1,090B CapEx peak in FY2022 corresponds to the revenue surge in FY2024-25; the NT$1,286B CapEx peak in FY2025 is expected to contribute to peak revenue in FY2027.

10.4 Layer 3: Capacity Utilization and ASP Trends

10.4.1 Advanced Node Utilization

TSM stated that advanced node capacity is "approximately one-third of AI demand" – meaning demand exceeds supply by about 3 times.

N2 Node Key Data:

• HVM initiated on 2026-01-02
• Yield 70-80%
• Initial capacity 40K wpm → 100K wpm by end of 2026 → 200K wpm by end of 2027
• Wafer Price: >$30,000/wafer (50%+ premium over N3's $20,000)
• 2nm cumulative revenue may surpass 3nm and 5nm in Q3 2026, becoming the most popular node

10.4.2 Mature Node Utilization

Mainland Chinese foundries (SMIC, etc.) are significantly expanding capacity at 28nm and above nodes, exacerbating overcapacity. TSM's strategy is to proactively reduce mature capacity (e.g., Fab14 cut by 15-20%) and reallocate resources to advanced packaging.

10.4.3 CoWoS Advanced Packaging Capacity

CoWoS Capacity Allocation:

• NVIDIA Share: >60% (2025-2026)
• Global CoWoS Supply (incl. outsourcing): Estimated ~150K wpm equivalent by end of 2026

10.4.4 ASP (Average Selling Price) Trends

When responding to market speculation of a 20% ASP increase, TSM management stated that "price is not the primary profit driver" – implying that the actual increase may be lower than market expectations, but structural ASP improvements (customers migrating to more advanced/expensive nodes) will continue to drive revenue growth.

10.5 Layer 4: Inventory Cycle Analysis

10.5.1 Global Semiconductor Inventory Overview

10.5.2 Key Customer Inventory Status

10.5.3 TSM Own Inventory Analysis

All inventory data from TSM's balance sheet.

Key Findings:

1. FY2025 inventory of NT$287B is largely flat with FY2024's NT$288B, but revenue increased by 33% → inventory/revenue ratio sharply dropped from 9.9% to 7.5%
2. DIO (TTM) of 69 days indicates healthy inventory management efficiency
3. Advanced node capacity is directly pre-booked by customers, eliminating the need to hold large amounts of finished goods inventory

10.5.4 Bullwhip Effect Risk Assessment

Bullwhip Effect Risk Rating: Medium (4/10). Reasons:

1. Risk-Mitigating Factors: TSM adopts a "build-to-order" model, with advanced node capacity pre-booked by customers for 1-2 years, not driven by inventory speculation
2. Risk-Increasing Factors: The growth rate of hyperscaler CapEx from $256B (2024) → $443B (2025) → $602B (2026) cannot be sustained indefinitely, and may face a slowdown in 2027-2028
3. Key Monitoring Indicator: If NVIDIA's days of inventory further increase from 130 days to 150+ days while revenue growth slows, the bullwhip effect warning will be upgraded

10.6 Layer 5: Terminal Demand Signals

10.6.1 AI Server/GPU Demand (Weight: 45%)

AI companies may invest over $500B in 2026 — a figure that was considered "impossible" two years ago.

Key Shift: Training → Inference

Inference workloads are projected to account for 2/3 of all AI computing in 2026, marking a structural shift from training-driven to inference-driven. The demand characteristics for chips in inference differ from training — requiring more medium-scale custom ASICs (rather than a few ultra-large GPUs), which implies (1) a broader customer base (not just NVIDIA), (2) more diversified wafer demand, and (3) potentially a more sustained demand cycle than purely training-driven demand.

10.6.2 Smartphones (Weight: 20%)

The overall mobile phone market is flat or even slightly shrinking, but its impact on TSM is limited: (1) Apple is one of TSM's largest customers, Apple's record shipments + iPhone 17 series will adopt N3/N2 → contributing stable demand for TSM's advanced nodes; (2) SoC upgrades for GenAI smartphones require more advanced processes + larger die sizes → increasing wafer area per device; (3) The dampening effect of rising DRAM prices on phone shipments is temporary (6-12 months).

10.6.3 PC/Notebooks (Weight: 10%)

AI PC penetration is soaring (31%→55%) but the overall market may shrink. Net impact on TSM: AI PCs adopt more advanced SoCs (both Intel/AMD use TSM's advanced nodes) → Increased wafer value per device offsets declining volumes. Overall assessment: Neutral to Positive.

10.6.4 Automotive Chips (Weight: 15%)

• Short-term (2026): Automotive chip demand recovery is slow, and mature node utilization remains low → slight drag
• Mid-to-long term (2027-2030): ADAS/autonomous driving upgrades + increasing EV penetration → driving dual demand for both mature and advanced nodes. TSM's German ESMC factory (28/22/16/12nm) is strategically positioned for this

10.6.5 IoT/Industrial (Weight: 10%)

IoT/Industrial semiconductors experienced an inventory digestion cycle in 2024-2025, with a moderate recovery expected to begin in H2 2026. The impact on TSM is concentrated in mature nodes (40nm-90nm), providing limited contribution but offering foundational support.

10.6.6 Terminal Demand Composite Score

The overwhelming strength of AI demand (9/10) compensates for the weakness in consumer electronics (smartphones/PCs) and industrial sectors. A weighted total score of 6.45/10 may seem modest, but the key is that AI demand directly consumes TSM's most profitable advanced node capacity, while weak consumer/industrial demand primarily impacts lower-margin mature nodes. A profit-weighted demand score could be as high as 8/10.

10.7 Layer 6: Composite Cycle Positioning Assessment

10.7.1 Four-Phase Framework Positioning

Current Position: Late-Mid Expansion

10.7.2 Six-Layer Signal Synthesis

10.7.3 AI Supercycle vs. Traditional Silicon Cycle: Coupling and Decoupling

10.7.4 Historical Comparable Analysis

The current memory shortage is referred to as "once in 40 years." Industry researchers define the current period as the "Semiconductor Gigacycle" — its scale and duration far exceeding traditional supercycles.

10.7.5 Risk Calendar: Cycle Turning Point Monitoring Indicators

10.7.6 Overall Assessment and Investment Implications

Key Conclusions:

1. Cycle Positioning: Mid-to-late expansion phase. Advanced nodes have entered a seller's market, while mature nodes are still recovering.

2. Key Differences from Traditional Cycles: This cycle is driven by AI infrastructure investment, characterized by an "arms race" – CapEx decisions by various HPC manufacturers are based on fear of missing out (FOMO) rather than pure ROI calculations. This makes the trigger conditions for CapEx downturns more stringent and the cycle duration potentially longer.

3. TSM's Unique Position: As the only manufacturer capable of simultaneously providing "advanced logic foundry + advanced packaging (CoWoS)," TSM holds the greatest pricing power and deepest moat in the AI supercycle. Its ROIC of 56.02% and gross margin of 59.9% are unmatched among semiconductor manufacturers.

4. Time Horizon: The optimal investment window is from now until 2027H1. Starting from 2027H2, close attention should be paid to peak signals such as slowing HPC CapEx growth and peaking memory prices.

5. Thermometer Calibration: The +0.795 "overheated" reading is consistent with a "mid-to-late expansion phase" positioning. The thermometer may reach +0.85-0.90 in 2026H2, corresponding to the "near peak" range. However, the structural characteristics of the AI Gigacycle suggest that the "peak" might be a sustained 1-2 year plateau rather than a traditional spike.

CQ2 Final Answer: CapEx return on investment is optimal under the current cycle positioning. FY2025 ROIC of 56.02%, CapEx/Revenue of 33.4% (downward trend), FCF +108.5% YoY. However, it should be noted: approximately 50%+ of FY2026E's $38-42B CapEx is allocated to N2 and CoWoS capacity expansion, with a return cycle of 18-24 months – meaning the full revenue contribution from this capacity will not be seen until FY2028. If 2028 coincides with a cycle slowdown, the return on this portion of CapEx might be lower than expected. It is recommended to closely monitor 2027 CapEx guidance – if management significantly raises it (>$45B), the risk of cycle overheating will escalate.

Chapter 11: In-depth Financial Analysis

11.1 Five-Year Revenue Growth Overview

TSMC achieved a historic growth trajectory from 2021-2025, with revenue increasing from TWD 1,587B to TWD 3,849B, a cumulative increase of 142.5%, and a CAGR of 24.7%.

Key Turning Point Analysis:

1. FY2022 Surge (+42.7%): Accelerated digitization post-pandemic + volume ramp-up of Apple M1/M2 series + automotive chip shortage windfall

2. FY2023 Pullback (-4.5%): The only year of negative growth, due to the consumer electronics inventory correction cycle (smartphone shipments -11.3%, PC shipments -16.2%)

3. FY2024-2025 Continuous Surge (+33.8%/+33.0%): AI supercycle initiated, explosive growth in NVIDIA H100/H200 demand, HPC revenue share jumped from 43% (FY2023) to 58% (FY2025)

11.2 Breakdown by Technology Node: Dominance of Advanced Process Technologies

11.3 Breakdown by Application Area: HPC Becomes the New King

FY2025 Revenue Structure (TWD B):

Key Insights:

1. HPC Super Cycle Validation: HPC grew from TWD 930B in FY2023 to TWD 2,232B in FY2025, representing a 56.0% CAGR over two years. This is not a simple cyclical recovery but a structural demand leap.

2. Smartphones Not a Drag: While smartphone revenue share appears to shrink from 39% to 27%, the absolute value still grew by 7.1%. This is a classic case of "slowing growth but solid foundation" – Apple's iPhone 15/16 series continues to contribute stable orders.

3. Automotive Business: Hidden Surprise: Automotive chip revenue growth was 32.5%, significantly higher than the overall growth of 33.0%. Although its share is small (5%), the quality of growth is high – automotive chips command high ASPs, strong customer stickiness, and long certification cycles, making it the second growth curve for the next 5 years.

11.4 By Customer Concentration: NVIDIA Surpasses Apple as Largest Customer

Significant Strategic Change: NVIDIA has for the first time surpassed Apple to become TSMC's largest customer.

Risks and Opportunities Coexist:

• Concentration Risk: The top 5 customers' share increased from 66% (FY2024) to 71% (FY2025E), indicating a deepening reliance on single customers (NVIDIA/Apple). Should NVIDIA's orders decline due to a slowdown in AI demand, the impact on TSMC would exceed that of the 2023 smartphone cycle.

• Enhanced Pricing Power: Despite high customer concentration, these are irreplaceable chip giants, granting TSMC absolute bargaining power. Price increases for two consecutive years in 2024-2025 (advanced nodes +3-5%, mature nodes +5-8%) have been well-accepted by customers.

11.5 Margin Analysis: Is 60% Gross Margin a Peak or a New Platform?

11.5.1 Gross Margin's Dramatic V-shaped Reversal

Deconstruction of Three Major Driving Factors Behind Five-Year Gross Margin Fluctuations:

Driving Factor 1: Product Mix (Contribution ~60%)

Core Logic: For every 10pp increase in advanced node share, gross margin improves by approximately 6pp. With advanced nodes comprising 70% in FY2025, this directly contributes to a gross margin increase of ~4.8pp.

Driving Factor 2: Pricing Power (Contribution ~25%)

TSMC has continuously raised prices in 2024-2025:

• N3 Node: 20-30% premium over N5
• CoWoS Packaging: 15-25% premium due to tight supply
• Mature Nodes: +5-8% in 2024, +3-5% in 2025

Pricing power stems from two main pillars:

1. Irreplaceable Technology: Advanced nodes (≤7nm) hold a 90% global market share, with no Plan B for customers.
2. Tight Supply-Demand: CoWoS capacity is expanding from 13K wpm in 2023 to 120-130K wpm by 2026, yet remains in tight supply.

Driving Factor 3: Scale Effect (Contribution ~15%)

Revenue grew from TWD 1.6T to 3.8T, with the fixed cost dilution effect contributing to a gross margin increase of ~3pp.

11.5.2 Deep Dive into FY2023 Gross Margin's 5.2pp Plunge

FY2023 gross margin fell from 59.6% to 54.4%, making it the only year of negative growth in five years. Three dragging factors:

1. Sharp Decline in Utilization Rate: FY2023 saw inventory correction in consumer electronics, with capacity utilization falling from ~95% in FY2022 to ~80-85%.

2. N3 New Node Learning Curve: In the initial ramp-up phase of N3 node mass production in 2023, yield rates were climbing (initial ~70%, mature phase >90%), dragging down overall gross margin by ~1-2pp.

3. Impact of USD Depreciation: The TWD/USD exchange rate moved from 30.7 (FY2022) to 31.6 (FY2023). With 80% of TSMC's revenue denominated in USD, foreign exchange losses impacted gross margin by ~0.5-1pp.

11.5.3 Q1 2026 Guidance 63-65%: Peak or New Platform?

TSMC's Q1 2026 gross margin guidance of 63-65% represents a continued increase from Q4 2025's 62.3%.

Bullish View: The New Platform Thesis

1. N2 Node Premium: N2 initiated High-Volume Manufacturing (HVM) on 2026-01-02, with initial customers including Apple A20 chips and NVIDIA Feynman architecture. N2 is expected to command a 15-20% premium over N3. If its share reaches 5-8% in Q1, it could contribute +1-1.5 percentage points (pp) to gross margin.

2. CoWoS Continued Tightness: CoWoS capacity for 2026 is 120-130K wpm, but demand from NVIDIA GB200/AMD MI400 still exceeds supply. CoWoS boasts a high gross margin of 70-75%; every 1pp increase in its share contributes +0.3-0.5pp to the overall gross margin.

3. Dilution Effect from Overseas Fabs Not Yet Evident: Although Arizona Fab 1 has started N4 mass production, its capacity share is <2%, with an impact on overall gross margin of <0.5pp. Significant dilution is only expected when Fabs 2/3 ramp up in 2027-2028.

Bearish View: Peak Theory

1. Risk of HPC Demand Peaking: If the AI super cycle slows down in H2 2026 (e.g., inference cost optimization driven by DeepSeek leading to decreased chip demand), the share of HPC could fall from 58% to 50%, dragging down gross margin by -2-3pp.

2. Price Competition Pressure: Samsung's 2nm mass production in 2026 (yield ~70%), Intel 18A in mass production. Although the technology still lags TSMC by 1-2 years, if customers (e.g., Qualcomm/MediaTek) diversify orders, TSMC may be forced to lower prices.

3. N2 Yield Ramp-Up Drag: N2's initial yield is 70-80%. If its share rapidly increases to 15-20% in 2026, learning curve costs could drag down gross margin by -1-2pp.

Quantitative Sensitivity Analysis:

11.5.4 Operating Profit Margin and Net Profit Margin: Better-than-Expected Profit Conversion Efficiency

Key Finding: FY2025 net profit margin of 45.1%, a new historical high. Conversion efficiency of 75.3% is significantly higher than the FY2021-2024 average of 72.4%.

Driving Factors Breakdown:

1. Decrease in Operating Expense Ratio: The operating expense ratio decreased from 10.4% in FY2024 to 9.1% in FY2025, saving TWD 50B.

   • Improved R&D Efficiency: R&D expenses were TWD 192B (+14.5% YoY). However, revenue growth of 33.0% significantly outpaced R&D growth, with R&D/Revenue decreasing from 6.8% to 5.0%.

   • SG&A Leverage Effect: SG&A expenses were TWD 159B (+18.2% YoY), with SG&A/Revenue decreasing from 4.6% to 4.1%.

2. Optimized Income Tax Rate: The effective tax rate decreased from 13.0% in FY2024 to 11.2% in FY2025, saving TWD 30B in taxes.

3. Increased Interest Income: Net cash of TWD 1,770B. Improved interest rate environment (Taiwan Central Bank benchmark rate at 2.0%), interest income contributed ~TWD 35B to net profit.

Quarterly Trend Validation:

Quarterly Acceleration Characteristics:

• Q4 2025 net profit margin of 48.4%, an increase of 2.7pp Quarter-on-Quarter (QoQ) from Q3, setting a new quarterly historical high.
• Q4 net profit of TWD 511B, a QoQ increase of 13.1%, with quarterly net profit exceeding TWD 500B for the first time.
• The conversion efficiency from gross margin to net profit margin reached 77.7% in Q4 (48.4%/62.3%), demonstrating extreme cost control.

11.6 Cash Flow Analysis: Real Cash Validation of Earnings Quality

11.6.1 Operating Cash Flow: Ultra-High Conversion Rate Validation

Five-Year OCF Trend:

Key Insights:

1. OCF/Net Income Ratio Declining Trend: Decreased from 1.88x in FY2021 to 1.37x in FY2025, but still well above the industry healthy benchmark of 1.0x. The decline is due to net income growth (193% CAGR) exceeding OCF growth (114% CAGR).

2. Stable Depreciation and Amortization as a Percentage of Revenue: Depreciation and amortization expenses/revenue remained in the 17-18% range, reflecting the fixed cost characteristic of the asset-heavy model.

3. Excellent Working Capital Management: The change in working capital in FY2025 was close to zero, meaning the growth in accounts receivable + inventory matched the growth in accounts payable, not tying up additional cash.

11.6.2 CapEx Analysis: Rational Return of the Super Investment Cycle

The Mystery of Declining CapEx Intensity:

FY2021-2022 represented TSMC's most aggressive CapEx cycle in history, with CapEx/Revenue reaching 48-53%, significantly exceeding the industry norm (30-35%). Why did it decrease to 33% in FY2024-2025?

Three Explanations:

1. Earlier Capacity Investments Paying Off: Fabs invested in during FY2021-2022 (e.g., N5/N4 capacity expansion, CoWoS production lines) entered their mass production return period in FY2024-2025, eliminating the need for duplicate investment.

2. Improved Capital Efficiency: Unit capacity investment costs for N3/N2 node fabs have been optimized. For example, the unit wafer investment cost for N3 fabs is 10-15% lower than N5, due to increased EUV lithography machine utilization.

3. Prudent Response to Cyclical Risks: After the FY2023 inventory correction cycle, management has become more cautious to avoid overcapacity. CapEx guidance has been adjusted from "unlimited to meet customer demand" to "matching revenue growth."

FY2025 CapEx TWD 1,286B Breakdown (Estimate):

Related CQ2: "TSMC's CapEx TWD 1.3T, can it generate sufficient returns over the next 5 years?"

→ We established a CapEx return model:

Conclusion: The CapEx payback ratio is extremely high, with cumulative FCF of TWD 2,988B over 5 years, meaning 57.6% of CapEx has been recovered. If the current growth rate is maintained from FY2026-2030, cumulative FCF will fully cover CapEx, achieving "self-financing."

11.6.3 Free Cash Flow: A Leap in Quality

Five-Year FCF Trend:

Key Characteristics:

1. FY2024-2025 FCF Surge: From TWD 287B (FY2023) → TWD 1,098B (FY2025), a two-year CAGR of 95.7%. This growth stems from the dual tailwinds of "high revenue growth + declining CapEx intensity."

2. FCF/Net Income Ratio of 63.2%: In FY2025, FCF accounted for 63.2% of net income, meaning that for every TWD 100 of net income earned, TWD 63 was converted into free cash flow. This ratio is extremely rare in asset-heavy industries (Intel ~30%, Samsung ~40%).

3. Stable Dividend Payout Ratio: FY2025 dividends were TWD 519B, with a dividend payout ratio of 29.9% (519/1,736), slightly below the historical average of 35%, retaining more cash for N2/A16 R&D + overseas fab construction.

FCF Allocation Bridge Diagram:

11.7 Balance Sheet: Fortress-Level Financial Health

11.7.1 Asset Structure: Strategic Significance of Asset-Heavy Model

FY2025 Balance Sheet Snapshot (TWD B):

Key Characteristics:

1. Very High Cash Ratio: Cash (TWD 2,760B) accounts for 34.9% of total assets, which is rare in capital-intensive industries. For comparison, Intel's cash accounts for ~15% of total assets, and Samsung's ~25%.

2. PP&E Accounts for 46.5%: Net property, plant, and equipment (TWD 3,681B) is TSMC's core moat. These fabs + EUV lithography machines + cleanrooms constitute a physical barrier that competitors cannot replicate in 5-10 years.

3. Current Assets/Current Liabilities = 2.62: The current ratio of 2.62 is well above the healthy benchmark of 1.5, indicating extremely strong short-term solvency.

11.7.2 Debt Structure: Leverage Choices for a Net Cash Company

Trend Analysis:

1. Accelerated Deleveraging: The D/E ratio decreased from 0.35 in FY2021 to 0.18 in FY2025, a 48.6% drop over 5 years. This deleveraging is due to the dual effect of "significant increase in shareholders' equity (retained earnings) + slight decrease in debt."

2. Net Cash at Historic High: Net cash in FY2025 is TWD 1,770B, equivalent to ~10% of market capitalization (TWD 1,770B / Market Cap TWD 18,430B). This cash reserve can support:

   • 1.4 years of CapEx without external financing (TWD 1,770B ÷ TWD 1,286B/year = 1.4 years)
   • Acquisition of competitors (e.g., GlobalFoundries, if geopolitical risks ease)
   • Stock buybacks in extreme circumstances (9.6% of current market cap could be repurchased)

3. Altman Z-Score 15.75: Well above the bankruptcy risk threshold of 3.0, placing it in the "extremely safe" zone.

Peer Comparison:

11.8 Profitability Metrics: The Golden Combination of ROE/ROIC

11.8.1 ROE Trend: The Value of 32.1%

DuPont Analysis (FY2025):

Key Insights:

1. Primarily Driven by Net Profit Margin: TSMC's excess ROE is mainly derived from its net profit margin of 45.1% (industry average 20-25%), rather than leverage (equity multiplier of 1.46x is lower than the industry average) or asset turnover (0.487x is lower than the industry average).

2. Heavy Assets Drag Down Turnover: The asset turnover of 0.487x is lower than the industry average because PP&E accounts for 46.5% of total assets. However, this is a "benign drag"—heavy assets themselves constitute a moat.

3. Low Leverage + High ROE Paradox: Typically, high ROE requires high leverage, but TSMC achieves a 32.1% ROE with extremely low leverage (D/E = 0.18), demonstrating the business's exceptionally strong profitability.

11.8.2 ROIC: Return on Invested Capital

ROIC Breakdown:

ROIC = NOPAT / (Shareholders' Equity + Interest-Bearing Debt - Excess Cash)

FY2025:

• NOPAT = Operating Profit × (1-Tax Rate) = TWD 1,956B × (1-11.2%) = TWD 1,737B
• Invested Capital = TWD 5,404B + TWD 990B - TWD 1,000B = TWD 5,394B (after deducting excess cash of TWD 1,000B)
• ROIC = TWD 1,737B / TWD 5,394B = 32.2%

ROIC 32.2% vs. Benchmark 24.9% Discrepancy: The benchmark calculation may not have deducted excess cash, leading to an overstated denominator. The 32.2% more accurately reflects the return on operating capital.

11.9 Quarterly Financial Acceleration Analysis

11.9.1 Revenue Quarter-over-Quarter: Exponential Acceleration

Seasonality Features:

• Q1 Off-Season: Q1 revenue accounts for 20-22% of full-year revenue, due to Chinese New Year and customer inventory adjustments. Q1 2025 QoQ -3.3% is consistent with seasonality.
• Q4 Peak Season: Q4 revenue accounts for 27-30% of full-year revenue, due to new iPhone stocking for Apple and year-end AI server demand. Q4 2025 revenue of TWD 1,056B breaks TWD 1T for the first time.

Signal of Slowing YoY Growth: Q4 2025 YoY +21.7%, a significant slowdown compared to Q1's +41.5%. Reasons:

1. Base Effect: H2 FY2024 revenue already saw high growth, increasing the YoY base for FY2025.
2. N3 Penetration Saturation: Q4 2025 N3 share at 24%, a slower growth compared to Q3's 22%.
3. Waiting for N2 Ramp-up: Some customers delayed orders until after N2 mass production in 2026Q2.

11.9.2 Gross Margin Quarterly Trajectory: A Milestone of Breaking 62%

Q4 2025 gross margin reached 62.3%, an increase of 2.8pp QoQ, setting a new single-quarter historical high. Driving factors:

1. Increased N3 Proportion: Q4 N3 proportion at 24% vs. Q3 22%, contributing +1.2pp to gross margin.
2. CoWoS Premium: Q4 CoWoS revenue proportion at ~18% (estimated TWD 190B), with a 15-25% premium contributing +0.8pp to gross margin.
3. Capacity Utilization Rate: Q4 capacity utilization rate at ~95%, nearing full capacity, maximizing fixed cost absorption.

11.10 Analyst Consensus Outlook: FY2026-2029 Growth Path

11.10.1 Analyst Consensus vs. Historical Performance

Trend Characteristics:

1. Decreasing Growth Rate but High Absolute Value: FY2026-2028 maintains 20-30% growth, slowing to 6.1% in FY2029. Reasons for slowdown could be:

   • AI super cycle entering maturity
   • Base effect (extremely high revenue base of TWD 7.3T in FY2029)
   • Competitors (Samsung/Intel) regaining market share

2. Expected Decline in Net Margin: Gradual decline from 45.1% in FY2025 to 43.6% in FY2029. Reasonable reasons:

   • Increased proportion of overseas fabs (Arizona Fab 2/3 mass production in FY2027-2028), diluting gross margin.
   • N2/A16 node learning curve costs
   • Price competition pressure

3. FY2029 Growth Cliff: EPS growth from +16.1% in FY2028 to +3.7% in FY2029, which warrants attention. This may reflect:

   • Analysts' doubts about the long-term sustainability of AI demand
   • Or small sample size for FY2029 data (only 10 analysts), leading to lower credibility

11.10.2 Key Assumption Testing

Analyst consensus implicit assumptions:

Sensitivity Analysis:

If actual FY2026 revenue is 10% below consensus (TWD 4,450B vs. TWD 4,945B), impact on valuation:

• Based on FY2026E P/E ~21x, a 10% revenue revision down → 15% EPS revision down (due to lower margins) → fair valuation revised down by 15-20%
• Current share price $355.41 × (1-17.5%) = $293 valuation reference (bear scenario)

11.11 Risk Warnings

1. NVIDIA Concentration Risk: Largest customer accounts for 22%, if NVIDIA cuts orders due to slowing AI demand, revenue could be impacted by 5-8 percentage points.

2. Overseas Fab Gross Margin Dilution: Arizona/Germany fabs' gross margins are 5-10pp lower than Taiwan's. When their proportion reaches 5-8% in FY2027-2028, it could drag down overall gross margin by 2-3pp.

3. Exchange Rate Risk: For every TWD 1 depreciation against USD, revenue increases by 3% but costs (imported equipment) increase by 1.5%, with a net impact of +1.5%. If TWD significantly appreciates, profit will be impacted.

4. Competitor Catch-up: Samsung 2nm mass production in 2026, Intel 18A yield improvement. Although still technologically behind, they might divert mid-to-low-end customers.

11.12 Financial Analysis Summary

CoWoS advanced packaging has transformed from a "technology demonstration" into TSM's strategic moat and revenue growth engine. This special topic reveals three key insights:

1. CoWoS is a margin-accretive business: Advanced packaging gross margin of 55-60% is close to the group's overall level, but capacity expansion CapEx efficiency far exceeds traditional foundries (CapEx per K wpm only $50-80M vs. $200-300M for foundries)

2. Capacity Allocation Politics Create Pricing Power: CoWoS demand exceeds supply by 15-20% until 2026, with NVIDIA holding a 60% share, creating "waiting list economics," allowing TSM to enjoy rare seller's bargaining power in the AI supply chain

3. SoIC to Reshape Value Curve: The bumpless 3D stacking technology (3μm pitch) slated for mass production in 2027 offers 3 times the interconnect density of CoWoS, opening up a **$50B+ new market** for logic-on-logic stacking for TSM

Chapter 12: Arizona/Overseas Fab Economics

12.1 Key Findings at a Glance

TSMC's (TSM) overseas expansion is at a critical turning point, shifting from "strategic commitment" to "high-volume mass production." Arizona Fab 1 has achieved 92% yield (surpassing Taiwan's parent fab by 4 percentage points), marking the complete shattering of the stereotype "high cost US fabs = poor quality." However, the operating cost premium for overseas fabs is real: 10% higher cost per wafer, coupled with 3 times the labor cost and 2-3 times the energy prices, leading to an anticipated gross margin dilution of 2-4% for 2025-2029.

Key Contradiction: In the short term, overseas expansion is "expensive insurance" – a $165B investment resulting in 2-3% gross margin erosion annually; in the long term, it is a "necessary strategic investment" – with customers willing to pay a "supply chain security premium" + narrowing geopolitical discount, which may begin to contribute positively to valuation starting 2027-2028.

This module is related to CQ6 (Geopolitical Risk Pricing) and CQ5 (Gross Margin Sustainability)

12.2 Global Fab Layout Overview

12.2.1 Status of Three Major Overseas Clusters (February 2026)

Arizona Cluster: $165B Flagship Project

Latest Developments:

• Fab 1(Fab 21 ): N4P/N5 has reached High Volume Manufacturing (HVM), with 92% yield, exceeding the Taiwan parent fab
• Fab 2(Fab 21 ): Equipment move-in advanced to Q3 2026 (July-September), with N3 mass production targeted for H2 2027 (1 year ahead of original schedule)
• Fab 3: Originally scheduled to start in 2028, rumored to be advanced to 2027, targeting 2nm/A16 process
• Fab 4-6: Gradually coming online in the 2030s, with a total planned 6 fabs

Capacity Targets:

• 2026: ~20K wpm (wafers per month)
• 2027: ~40K wpm (Fab 2 online)
• 2030: Target 100K+ wpm (all 6 fabs operational)

CHIPS Act Subsidies:

• Direct Grants: $6.6B
• Low-Interest Loans: $5B
• 25% Investment Tax Credit: Estimated **$16.5B** (based on $66B initial investment × 25%)
• Total Subsidy Value: ~$28B (17% of total $165B investment)

JASM Kumamoto: Strategic Upgrade from 6nm to 3nm

Current Status:

• Process: 12nm/16nm/22nm/28nm
• Customers: Sony (image sensors), Denso (automotive chips)
• Capacity: Already in mass production, but heavy equipment to be removed in 2026 + suppliers notified no new tools needed for the entire year

Major Upgrade:

• Process: Upgraded to 3nm from the original 6nm/7nm
• Timeline: Equipment move-in later in 2026, mass production targeted for end of 2027
• Investment (for two fabs): Totaling ~$20B (Japanese government subsidy approximately 50%)
• Strategic Significance: Japan becomes the first 3nm manufacturing base outside Taiwan, serving local customers such as Sony/Toyota/Honda

ESMC Germany: European Hub for Automotive/Industrial Chips

Project Overview:

• Equity Structure: TSMC 70%, Bosch 10%, Infineon 10%, NXP 10%
• Process: 28nm/22nm/16nm/12nm (mature process, serving automotive/industrial)
• Capacity: 40K wpm
• Investment: €10B (~$10.8B), EU + German government subsidies **~€5B (50%)**
• Timeline: Groundbreaking August 2024, equipment move-in H2 2026, mass production end of 2027

Strategic Positioning: Localization of the European automotive industry supply chain – Bosch/Infineon/NXP, the three shareholders, are themselves among the top 5 customers for automotive semiconductors, making ESMC equivalent to a "customized fab."

12.2.2 Capacity Share Evolution Path

Capacity Share Estimation:

12.3 Overseas Fab Economic Model: Cost Structure Breakdown

12.3.1 Unit Cost Comparison: Taiwan vs Arizona vs Japan vs Germany

Arizona Cost Breakdown

TechInsights Conclusion: Cost per wafer is only 10% higher than in Taiwan, significantly lower than the earlier expectation of 30-50%.

Cost Composition Analysis:

: Equipment cost accounts for up to 70% (ASML lithography machines, Applied Materials etching machines, etc., are uniformly priced globally), offsetting the impact of a threefold difference in labor costs. Labor accounts for only 2% of total costs; even if wages triple, it would only increase total costs by 4%.

Net Cost After Subsidies:

• Before Subsidies: +10%
• CHIPS Act 25% Tax Credit: Equivalent to 25% CapEx reduction, 17.5% reduction in depreciation cost (70%×25%)
• Net Cost Premium After Subsidies: ~-3% to +5% (depending on depreciation and amortization period)

Japan/Germany Cost Comparison

JASM Japan:

• Labor Cost: Approximately 1.5-2 times that of Taiwan (Japanese engineer annual salary $80-120K vs Taiwanese $50-70K)
• Energy Cost: Similar to Taiwan (Japanese government subsidizes 50% of project costs, including energy incentives)
• Estimated Unit Cost Premium: +5-8%
• After Subsidies: Japanese government subsidizes 50%, net cost may be 5-10% lower than Taiwan

ESMC Germany:

• Labor Cost: Approximately 2-2.5 times that of Taiwan (German engineer annual salary €90-140K ≈ $100-155K)
• Energy Cost: 2-3 times that of Taiwan (high electricity prices in Europe)
• Estimated Unit Cost Premium: +15-20%
• After Subsidies: EU subsidies €5B (50%), net cost premium +5-10%

12.3.2 Arizona Fab Economic Model Case Study

Modeling with Fab 2 (N3 process, 40K wpm) as an example:

Inputs:

• CapEx: $28B (Fab 2 standalone investment, estimated from $165B/6 fabs)
• CHIPS Act Subsidies: -$1.1B (direct grants) -$7B (25% tax credit) = Net Investment $19.9B
• Equipment Life: 5 years (rapid depreciation for advanced process equipment)

Outputs:

• Capacity: 40K wpm = 480K wafers/year
• N3 Average Selling Price: $16,000/wafer
• Annual Revenue: 480K × $16,000 = $7.68B

Operating Costs:

• Taiwan Unit Cost: $6,000/wafer
• Arizona Cost Premium: +10% → $6,600/wafer
• Adjustment After Subsidies: -3% → $6,400/wafer
• Annual Operating Cost: 480K × $6,400 = $3.07B

ROI Calculation:

• Annual Gross Profit: $7.68B - $3.07B = $4.61B
• Gross Margin: 60% (vs 62.5% for Taiwan fabs)
• CapEx Payback Period: $19.9B / $4.61B = 4.3 years
• IRR (10-year cycle): ~18% (vs 22% for Taiwan fabs)

: A 4.3-year payback period + 18% IRR is considered an acceptable level for the capital-intensive semiconductor industry, but it is noticeably lower than Taiwan fabs. The core logic is "strategic necessity > pure financial return".

12.4 Gross Margin Dilution Modeling: Quantifying Impact Pathways

12.4.1 TSM Official Guidance vs Actual Impact

Official Guidance Evolution:

• 2024 Q4: Expected gross margin dilution of 2-3% (early) → 3-4% (later) for 2025-2029
• 2025 Q2: Revised to 1-2% (2025) → 2-3% (2026-2027) → 3-4% (2028+)
• 2026 Q1 (Latest): Gross margin guidance 63-65% (midpoint 64%), an increase of 4 percentage points compared to FY2025's 59.9%

: Arizona yield ramp-up exceeded expectations (92% vs original expectation of 85-88%) + customer acceptance of price increases (N3 prices 60% higher than N5) + delayed overseas capacity share (only 4% in 2026 vs original expectation of 8%).

12.4.2 Annual Dilution Impact Breakdown

Modeling Assumptions:

1. Taiwan fab gross margin baseline: 64% (2026 guidance midpoint)
2. Overseas fab gross margin: 55-58% (cost premium 10% + yield loss 2-3%)
3. Capacity Share: See Table in Section 1.2

Calculation Formula:

: The model above shows a dilution of 32-62 bps for 2026-2027, which is largely consistent with TSM's official guidance of "1-2%→2-3%" (100 bps = 1%).

Sensitivity Analysis: If overseas fab gross margin increases to 60% (closer to Taiwan level):

1. Yield consistently at 92%+ (already achieved)
2. Scale effect reduces per capita cost by 15%
3. Customers accept "supply chain security premium", N3/N2 overseas foundry prices +5-10%

12.4.3 Absolute Gross Profit Impact: Dilution ≠ Profit Decline

Key Counterintuitive Finding: While gross margin percentage dilutes, the absolute gross profit amount may increase.

2027 Scenario Projection:

• Total Revenue: $95B (YoY +15%, AI-driven)
• Net Gross Margin: 63.4% (62 bps dilution)
• Gross Profit Amount: $95B × 63.4% = $60.2B
• vs 2026 (assuming $82B revenue × 63.7%): $52.2B
• Gross Profit Amount Growth: +$8B (+15.3% YoY)

12.5 Benchmarking Analysis: Intel/Samsung/GlobalFoundries Overseas Expansion

12.5.1 Intel Ohio: The "IDM2.0" Gamble

Project Scale:

• Investment: $20B+
• CHIPS Act: $8.5B direct grants + $11B loans = $19.5B subsidies (nearly 100%!)
• Process: Intel 18A (benchmarking against TSMC 2nm)
• Timeline: Mass production 2027-2028

Comparison with TSM:

: Intel received nearly "full government funding", exposing its questionable business viability — If Intel's 18A foundry business can be profitable, why does it need a 97% subsidy? In contrast, TSMC only needs a 17% subsidy to advance its $165B investment.

12.5.2 Samsung Texas: Challenges of 2nm First-Mover Advantage

Project Scale:

• Investment: $17.3B (Taylor fab)
• CHIPS Act: $4.75B Direct Grant
• Process Technology: 2nm GAA (Gate-All-Around)
• Timeline: Trial Production by End of 2026 (6-12 months earlier than TSMC)

Progress Risks:

• Samsung's 3nm yield has been consistently below 60% (vs TSMC N3's 70%+)
• 2nm trial production ≠ volume production; TSMC, though starting later, may achieve HVM sooner
• Clients: Qualcomm previously shifted orders to TSMC due to Samsung's 3nm yield issues; whether 2nm can win them back is uncertain

12.5.3 GlobalFoundries: The "Safe Bet" in Mature Process Technologies

Strategy: Abandoning advanced process technologies (below 14nm), focusing on 28nm/22nm/12nm mature processes.

CHIPS Act: $1.5B (for New York/Vermont fab expansion)

Comparison with TSMC ESMC: Both target mature process technologies, but TSMC holds an advantage with its technological superiority (FinFET 12nm vs GF's planar 12nm) and client base (Bosch/Infineon/NXP shareholder ties).

12.5.4 Summary: TSM's Overseas Expansion: Optimal "Quality-to-Efficiency Ratio"

Subsidy Efficiency Ranking:

1. TSMC: $4.2B/fab subsidy, confirmed clients, verified yield ✅
2. Samsung: $4.75B/fab subsidy, high 2nm technology risk ⚠️
3. Intel: $9.75B/fab subsidy, foundry business model unproven ❌

: TSMC's overseas expansion is the project "least reliant on subsidies"; even if the CHIPS Act is cut by 50%, its economic viability remains feasible. Intel/Samsung have high dependence on subsidies, facing significant policy change risks.

12.6 Quantifying Geopolitical Risk Hedging Value

12.6.1 The "Insurance Value" Framework

The true value of overseas capacity lies not in ROI, but in reducing the valuation discount caused by a Taiwan Strait crisis.

Geopolitical Discount Model:

• Current TSM valuation implies geopolitical discount: 15-25% (compared to a no-geopolitical-risk scenario)
• Probabilities of three Taiwan Strait scenarios: Grey Zone 55-65%, Blockade 8-12%, Full-scale Conflict 3-5%
• Expected Loss = ∑(Scenario Probability × Revenue Loss)

Overseas Capacity Hedging Effect:

Specific Impact on Valuation:

• Current Market Cap: $950B (Assuming Feb 2026)
• Geopolitical discount of 20%: Implied "risk-free" fair value $1,188B
• Discount narrows to 16% in 2027: Fair Value $1,131B → Stock Price Upside 19%
• Discount narrows to 12% in 2030: Fair Value $1,080B → Cumulative Upside 14%

12.6.2 The "Supply Chain Security Premium" Clients are Willing to Pay

Case Evidence:

1. Apple: Has committed to procuring N4P chips from Arizona Fab 1 (A16 Bionic backup capacity), did not request a discount
2. NVIDIA: Blackwell GPUs produced in Arizona, accepts full price once yield matches Taiwan
3. AMD: Publicly stated 20% production cost savings in Arizona (logistics + tariff optimization)

:

• For Apple/NVIDIA, wafer costs represent only 15-25% of iPhone/GPU BOM
• A 6-month supply disruption due to a Taiwan Strait crisis → hundreds of billions of USD in lost iPhone/GPU revenue
• Paying a 5-10% wafer premium for supply chain resilience is "extremely low-cost insurance"

Premium Pricing Calculation:

• If TSM marks up overseas fab products by 5%:
  • 2027 Overseas Revenue: $95B × 8.8% = $8.4B
  • Premium Revenue: $8.4B × 5% = $420M
  • Offsetting GM dilution: +44 bps (equivalent to offsetting 70% of 62 bps dilution)
• If marked up by 10%:
  • Premium Revenue: $840M → +88 bps → fully offsets dilution and contributes positively

12.7 Cultural Challenges and Operational Risks: An In-depth Analysis of the Arizona Case

12.7.1 The Truth Behind the "Anti-American Culture" Controversy

Issues Revealed:

• Employee Turnover: Approximately half of American engineers resigned during Taiwan training
• Lawsuit: 13 former employees sued TSM for "anti-American culture," alleging Asian employees received preferential promotions
• Cultural Conflicts: Taiwanese engineers accustomed to "same-day overtime notification," American employees refused weekend on-call duty

TSM's Countermeasures:

1. Localized Training: Expanding Arizona training facilities, reducing the need for Taiwan-bound training
2. Recruitment Scale: Apprentice program expanded to 200 people by 2026 (vs 16 in 2023)
3. Compensation Adjustment: American engineers' annual salary $100-150K (30-50% higher than Taiwan)
4. Partner Institutions: Collaborating with Arizona State University (ASU) and Grand Canyon University to cultivate technicians

Effectiveness Assessment:

• 92% yield proves that "American employees are inferior to Taiwanese" is a false premise
• However, cultural integration requires 5-10 years, and short-term friction is unavoidable
• In the long run, Arizona may form a "Taiwanese-American hybrid" management model (similar to Toyota's US factories)

12.7.2 Quantifying Operational Risks

Incidents Occurred:

• Gas Supply Interruption: 2024 Arizona Fab 1 specialty gas supplier malfunction → temporary yield drop to 80% → recovered to 92% within 2 weeks

List of Potential Risks:

1. Talent Shortage: US semiconductor engineer shortage of 40,000 (by 2030)
2. Long Supply Chain: Chemicals/spare parts shipped from Asia → Lead time Taiwan 3 days vs Arizona 14 days
3. Policy Fluctuations: If CHIPS Act funding is cut/scrutinized, it could affect the expansion pace

Risk Hedging:

• TSM has requested Applied Materials/ASML to establish spare parts centers in Arizona
• Signed long-term gas supply agreements with Air Liquide/Linde (redundant suppliers)

12.8 Related Analysis

12.8.1 CQ6: How is Taiwan Strait Geopolitical Risk Priced?

Module Contribution:

• Quantified the "insurance value" of overseas capacity: Every 10% share → geopolitical discount narrows by 4% → valuation increases by $38B
• Validated the "diversification reduces risk" hypothesis: 20% overseas capacity by 2030 could allow 85-90% revenue retention during a crisis
• Provided a path for narrowing the geopolitical discount: 20% in 2026 → 12% in 2030 → <10% in 2035

To Be Verified:

• Under three scenarios of a Taiwan Strait crisis, can overseas fabs truly operate independently (supply chain/talent/technology licensing)?
• If mainland China prohibits the export of critical materials (photoresist/sputtering targets) to Taiwan, can Arizona/JASM substitute?

12.8.2 CQ5: Gross Margin Sustainability?

Module Contributions:

• Dissected the year-over-year impact of overseas expansion on gross margin: -32 bps in 2026 → -110 bps in 2030
• Demonstrated "dilution is manageable": Even with overseas share at 18.4% in 2030, gross margin remains at 62.9% (above industry average of 55%)
• Identified hedging paths: Customer premiums of 3-5% can fully offset dilution

To Be Integrated:

• Can the gross margin of N2/A16 processes reach 65%+ (offsetting overseas dilution)?
• Can the gross margin contribution of CoWoS advanced packaging increase from 5% to 10% (compensating for fab dilution)?

Chapter 13: CoWoS Packaging Economics

13.1 Three Generations of CoWoS Technology Comparison

Technical Differentiation :

• CoWoS-S: Single silicon interposer achieves high-speed chip-to-chip interconnection via TSVs, area limited to 3.3X reticle size (~2700mm²), suitable for high-end AI chips
• CoWoS-L: Uses LSI (Local Silicon Interconnect) chips for local interconnect bridging + organic substrate RDL layer for power/signal distribution, 20-30% lower cost than CoWoS-S while supporting larger areas (currently 3.5X, 2027 target 9X reticle size)
• InFO: Fan-Out packaging, no substrate required, chip directly embedded in resin molding, lowest cost but poor thermal dissipation (low thermal conductivity of resin), not suitable for high-power AI chips

NVIDIA Blackwell B100/B200 adopts CoWoS-L, AMD MI355/MI400 also chose CoWoS-L, indicating that flexibility (large size) + cost optimization has become the preferred balance point for customers, and CoWoS-S is being pushed towards the ultra-high-end niche market.

13.2 CoWoS Cost Structure Analysis

Analyzing the economics of advanced packaging using NVIDIA B200 as an example:

Key Findings:

1. Advanced packaging accounts for over 60% of die manufacturing cost: The $1,100 packaging cost represents 61% of the $1,800 GPU die cost, breaking the traditional perception that "packaging is a secondary cost"

2. HBM + Packaging accounts for 63% of total cost: The combined total is $4,000; TSM secures the largest share of the AI chip value chain through its monopolistic CoWoS technology

3. Immense Gross Margin Potential: B200 selling price $30K-35K vs. cost $6.4K, a 470-450% gross profit markup; even a 20% increase in CoWoS price (an incremental cost of $220) would still be acceptable for NVIDIA

13.3 The Capital Efficiency Miracle of Capacity Expansion

13.3.1 2023-2026 Capacity Growth Trajectory

Growth Rate: 13K(2023)→130K(end of 2026) = 10x growth in 3 years, CAGR 115%

Capacity Allocation Forecast (130K wpm for 2026) :

Search results do not indicate Apple's confirmation of using CoWoS for M-series. However, given the multi-die design requirements of M4 Ultra and Apple's strategic importance to TSMC, reserving 5% of capacity (6.5K wpm) is reasonable. The actual proportion may be in the 3-7% range.

13.3.2 CapEx Efficiency Comparison: CoWoS vs. Traditional Foundries

TSM Capital Expenditure Structure for 2026 :

• Total CapEx: $52-56B (vs. 2025 $40.9B, +27-37% YoY)
• Advanced Packaging Allocation: 10-20% → $5.2-11.2B
• CoWoS Capacity Increase: 75K→130K wpm = +55K wpm

Estimated Investment Intensity per Unit Capacity :

$$
\text{CoWoS Investment per K wpm} = \frac{$5.2B - $11.2B}{55K \text{ wpm}} = $95M - $204M \text{ per K wpm}
$$

Compared to Traditional Foundries :

• 5nm/3nm Foundries: $200-300M per K wspm (wafer starts per month)
• CoWoS Packaging Facilities: $50-120M per K wpm (considering shared facility amortization)

ROI Cycle :

• Foundries: 5-7 years to reach breakeven (considering technological iterations + depreciation)
• CoWoS Facilities: 3-4 years to recoup investment

Conclusion: CoWoS is a more capital-efficient growth engine, where every $1B invested can add 8-20K wpm of capacity, quickly converting into revenue in a high demand environment.

13.4 Revenue and Profitability Analysis

13.4.1 Evolution of Advanced Packaging Revenue Share

Historical Trends :

• CoWoS Capacity 130K wpm × Assumed ASP $15K per wafer × 85% Utilization × 12 Months = $19.9B Theoretical Ceiling
• However, CoWoS only accounts for 80% of advanced packaging (the other 20% being InFO/SoIC), so CoWoS Revenue ~$16B
• Considering capacity ramp-up + customer mix, actual revenue is in the $12-15B range, accounting for 10-13% of total revenue

Growth Drivers :

1. AI Accelerator Demand Explosion: NVIDIA to ship 2 million Blackwell units in 2026 (vs. 1 million Hopper units in 2025), with each B200 consuming 1 CoWoS wafer
2. Customer Diversification: Broadcom ASIC from 50K wpm in 2024 → 150K wpm in 2026 (3x growth), AMD MI series capturing 10%+ share
3. ASP Increase: Tight CoWoS-L demand, TSM has the pricing power to increase prices by 20%

13.4.2 Advanced Packaging Gross Margin Analysis

Official Guidance :

• TSM Overall Gross Margin: 59-61% (2026E high-end guidance)
• HPC Business Share: >60%, the main driver supporting gross margin
• Source of Pricing Power: N3/N5 node price increase 5% + CoWoS supply-demand gap 15-20%

• Assumption 1: HPC business gross margin 62% (2ppt higher than group average), due to combination of 3nm die + CoWoS packaging
• Assumption 2: CoWoS standalone gross margin 55-60%
  • High technical barrier (difficult yield control, large-size LSI + multi-layer RDL)
  • Capacity sold-out until 2026, no price competition pressure
  • Strong customer lock-in effect (high switching costs, see Section 3.3)
  • However, lower than wafer foundry 65-70% gross margin (as packaging involves more material costs such as organic substrates/copper pillars)

Comparison: ASE/Amkor's OSAT Model :

• Traditional OSAT Gross Margin: 20-25%
• TSM achieves a 30-35ppt premium through vertical integration (wafer + packaging one-stop service), confirming CoWoS as a high-value business

13.4.3 "Waitlist Economics" and Customer Lock-in

Current CoWoS Supply-Demand Gap Status :

Customer Lock-in Mechanism :

1. Technological Lock-in: CoWoS customers require a 12-18 month design cycle (chip layout + thermal simulation + TSV/LSI interface design); switching to Samsung I-Cube/Intel Foveros means restarting tape-out

2. Capacity Lock-in: TSM has signed multi-year capacity commitment agreements with NVIDIA/Broadcom, ensuring priority supply, at the cost of customers being unable to easily switch orders

3. Ecosystem Lock-in: HBM suppliers (SK Hynix/Micron) have already optimized stacking solutions for TSM CoWoS; switching packaging vendors requires HBM suppliers to adjust synchronously

Quantification of Switching Costs :

Conclusion: Even if Samsung/Intel offer a 20% discount on CoWoS, NVIDIA would still choose TSM, because time cost >> price difference. This is the foundation of TSM's pricing power, allowing for a 20% price increase.

13.5 Competitive Landscape: How Wide is TSM's Moat?

13.5.1 Comparison of the Three Giants: TSM CoWoS vs Samsung I-Cube vs Intel Foveros

Market Share Estimate (2026 Global AI Chip Advanced Packaging) :

• TSM CoWoS: 70-75% (90K wpm of 130K for AI chips)
• Samsung I-Cube: 5-8% (Baidu Kunlun chips only + small number of test customers)
• Intel Foveros: 10-12% (Intel's own Ponte Vecchio + external ASIC orders)
• Others (ASE/Amkor Standalone Solutions): 8-12%

13.5.2 Samsung I-Cube: Looks Similar, Why Did It Lose Market Share?

Technology Comparison :

Analysis of Samsung's Failure :

1. Yield Disadvantage: I-Cube yield rate of 60-70% vs TSM CoWoS 85-90%, leading to 15-20% higher costs

2. Insufficient Capacity Investment: Samsung's advanced packaging CapEx for 2023-2025 is only $2-3B (vs TSM $8-12B), with capacity only 1/5 of TSM's

3. Wavering Strategy: Samsung Foundry is simultaneously promoting GAA wafer technology + I-Cube packaging, dispersing resources; TSM, on the other hand, is all-in on CoWoS capacity expansion

4. HBM Supply Chain Disadvantage: Although Samsung is an HBM supplier, SK Hynix monopolizes NVIDIA HBM orders, and Samsung I-Cube cannot provide the integrated advantage of HBM+packaging

Conclusion: I-Cube technology is feasible, but the overall lagging in ecosystem + execution + timing has led to its marginalization. Samsung missed the 2020-2023 AI chip takeoff window, and there is no possibility of reversal by 2026.

13.5.3 Intel Foveros: The Double-Edged Sword of Vertical Integration

Technical Differentiation :

• Foveros Direct: Utilizes hybrid bonding to achieve direct die-to-die connection, with an interconnect density of 10μm pitch (vs CoWoS's 25-40μm), theoretically offering superior performance
• Application Scenarios: Logic-on-logic 3D stacking (e.g., Intel Meteor Lake's Compute tile + SoC tile)

Market Positioning :

1. Intel Priority: 60%+ of Foveros capacity is used for Intel's own CPU/GPU, limiting large-scale adoption by external customers
2. ASIC Supplementary Market: In situations where TSM CoWoS is sold-out, second-tier cloud vendors (non-NVIDIA/AMD) are attempting Foveros
3. Price Disadvantage: As an IDM, Intel needs to cover full wafer + packaging costs, making its pricing 10-15% higher than TSM's outsourcing model

Why Can't It Shake TSM?

• Intel needs Foveros to support its own product roadmap, so its capacity cannot guarantee long-term supply to external customers
• Customers are concerned about competitive conflicts with Intel's CPU/GPU business (e.g., AMD would not use Intel packaging)
• Foveros's ecosystem is closed, lacking third-party cooperation networks like ASE/Amkor

13.6 OSAT Collaboration Model: Accelerator for Expansion

13.6.1 TSM + ASE + Amkor Tripartite Division of Labor

Outsourcing Strategy :

Division of Labor Model :

TSM Retains Core Technology :

• Not Outsourced: LSI chip manufacturing, TSV process, RDL fine routing (these are CoWoS's core IP)
• Outsourced: Labor-intensive + equipment-intensive back-end assembly (ASE/Amkor have cost advantages)

13.6.2 The Economics of OSAT: Why are ASE/Amkor Willing to Collaborate?

ASE's Benefits :

• Potential Orders in 2026: 130K wpm × 40% outsourcing rate × 30% back-end value × $15K ASP = $2.3B Revenue
• Gross Margin Improvement: CoWoS back-end gross margin of 30-35% (vs traditional packaging 20-25%), due to TSM premium + technical complexity
• Strategic Value: Binding with TSM = Securing an entry ticket into the AI supply chain, ASE stock price increased 120% from 2023-2025 (vs Philadelphia Semiconductor Index 80%)

Amkor's US Strategy :

• $7B Arizona Factory: Supports TSM Arizona 3nm fab, providing local packaging (meeting NVIDIA/Apple defense-grade "Made in USA" requirements)
• Intel Collaboration: Simultaneously undertaking Intel EMIB orders, diversifying customer risk
• Geopolitical Premium: US government CHIPS Act subsidies of $1-2B, reducing Amkor's investment risk

Competition Relationship Management :

• ASE/Amkor do not develop competitive CoWoS technology (having signed non-disclosure agreements), and only execute TSM-specified processes
• TSM gains capacity flexibility through outsourcing, without needing to self-build all back-end capacity (CapEx savings of $3-5B)
• Tripartite Win-Win: TSM focuses on technology R&D + high-value front-end processes, while OSAT obtains stable high-gross-margin orders

13.7 SoIC 3D Stacking: Next-Generation Growth Engine

13.7.1 SoIC vs CoWoS: Technical Generational Leap

SoIC Key Technical Breakthroughs :

1. Hybrid Bonding: Copper-to-copper direct bonding (no micro-bumps required), interconnect density increased by 3-10 times

   • CoWoS: 25-40μm pitch (limited by bump size)
   • SoIC-P 2026: 16-25μm pitch
   • SoIC-X 2027: 3μm pitch (vs Intel Foveros Direct 10μm)

2. Heterogeneous Node Stacking:

   • 2026: N3 top chip + N4 bottom chip (0.2 reticle size)
   • 2027: A16(1.6nm) top + N2(2nm) bottom (full reticle size)

3. Thermal Management Advantage: Chips in direct contact (vs CoWoS interlayer), heat dissipation efficiency increased by 30-40%

13.7.2 SoIC Market Scale and Application Scenarios

Mass Production Timeline :

• 2023: SoIC entered small-volume production (next-gen AI products)
• 2024-2026: Capacity CAGR >100% (growing from a very small base)
• 2027: Target 30 SoIC designs in mass production

Target Market :

The above TAM assumes SoIC will replace 30-50% of the CoWoS market and open up new applications (CPU/GPU 3D stacking) between 2027 and 2030, based on TSMC's historical penetration rate for InFO/CoWoS (achieving market dominance in 5 years). This is an optimistic but achievable scenario.

13.7.3 SoIC's Significance in TSMC's Valuation Restructuring

CoWoS Ceiling Predicament :

• CoWoS primarily serves the AI accelerator market, with TAM limited by data center GPU/ASIC demand ($80-100B by 2028)
• Single customer dependency: NVIDIA accounts for 60%, posing high customer concentration risk

SoIC Opens New Battlefield :

1. Penetrating Mainstream CPU/GPU Market: If Intel/AMD's x86 CPUs (300-400 million units shipped annually) adopt SoIC, TSMC gains a new revenue pool of $30-50B
2. Reducing Customer Concentration: From 60% reliance on NVIDIA → diversified to a balanced distribution across four major customers: Apple/Intel/AMD/NVIDIA
3. Widening Technology Gap: Samsung/Intel's Foveros hovers at 10μm pitch, while TSMC will reach 3μm by 2027 = 3x density advantage, widening its moat

Impact on SOTP Valuation :

• Traditional Model: Advanced packaging valued at 15-18x P/E (vs. wafer foundry at 20-25x), as it's considered a "mature business"
• SoIC Revaluation: If 3μm mass production + 30 design wins are proven by 2027, advanced packaging should command a growth business multiple of 20-25x P/E, similar to new nodes like 3nm/2nm
• Incremental Valuation: SoIC contributing $10-15B revenue × 55% gross margin × 22x P/E in 2028-2030 = $120-180 billion incremental market capitalization

13.8 Strategic Implications of CoWoS Economics

13.8.1 Pricing Logic for Advanced Packaging in SOTP

Current Market Valuation Split for TSMC :

New Model After CoWoS Revaluation :

Revalued Advanced Packaging Segment Market Cap:
$$
($12B × 1.4) × 58% × 20x = $195B \text{ (vs Old Valuation $99B, +97%)}
$$

1. By 2026, TSMC demonstrates a 20% price increase for CoWoS and customer acceptance (NVIDIA/Broadcom contract renewal)
2. By 2027, at least 20 of the 30 SoIC mass production designs are successful (yield >80%)
3. At least one of Apple/Intel publicly announces adoption of SoIC for mainstream products

13.8.2 Three Key Questions for Investors

KQ1: Does CoWoS dilute overall gross margin?

No, CoWoS is a margin-accretive business:

• CoWoS gross margin of 55-60% is close to the group's overall 59-61%, and is on an upward trend (capacity crunch + pricing power)
• Compared to InFO's first mass production in 2020 when gross margin was only 40-45%, CoWoS starts at a higher point
• With the inclusion of SoIC (higher technical barrier), advanced packaging gross margin is expected to reach 62-65%

KQ2: Does NVIDIA's 60% share constitute a risk?

Risk Aspect:

• If NVIDIA builds its own packaging plant by 2027 (similar to Intel Foveros), TSMC loses its largest customer
• If the AI bubble bursts, NVIDIA's demand is halved, leading to CoWoS overcapacity

Moat Aspect :

• NVIDIA building its own packaging requires $10-15B CapEx + 3-5 years of technical accumulation, vs. the opportunity cost of directly using TSMC (missing 2-3 product generations)
• Even if AI demand falls by 50%, the remaining market still requires 65K wpm of CoWoS capacity (vs. TSMC's 2024 baseline of 40K), indicating a slowdown, not a collapse
• Conclusion: The 60% share in 2026-2028 is a feature, not a flaw, as TSMC is the only supplier capable of meeting NVIDIA's scale requirements

KQ3: How long will it take for Samsung/Intel to catch up?

At least 3-5 years:

• 2026-2027: TSMC absolute monopoly (75%+ market share)
• 2028-2029: Samsung I-Cube captures 10-15% share (mainly from tier-2 customers + price-sensitive markets)
• 2030+: If Intel spins off its Foundry business and opens Foveros, it might capture 20% of the market; however, TSMC will have already moved to SoIC 2.0, maintaining its technological lead

13.9 Risks and Counterarguments

13.9.1 Bearish Argument 1: Unsustainable AI Demand

Arguments :

• Generative AI profitability model unproven, OpenAI/Anthropic's cash burn unsustainable
• Cloud providers' CapEx peaks in 2027, NVIDIA GPU demand halved
• CoWoS overcapacity, TSMC forced to cut prices

Rebuttal :

• Diversified Demand: In 2026, NVIDIA accounts for 60%, but Broadcom (15%) + AMD (11%) = 26% comes from non-NVIDIA, and the growth rate is faster (CAGR 40% vs NVIDIA 25%).
• Application Expansion: AI is expanding from training (H100) to inference (B100) to edge computing (Jetson CoWoS version), indicating deeper demand layers.
• Even if Demand Halves: 65K wpm (half of 130K in 2026) is still higher than the 2024 base of 40K, meaning TSM's growth is merely slowing, not a revenue decline.

Searching for "Polymarket AI bubble burst 2026" did not yield relevant prediction markets, indicating low market consensus on an AI collapse.

13.9.2 Bearish Argument 2: Geopolitical Impact on Taiwan's Capacity

Argument :

• Taiwan Strait conflict leads to CoWoS capacity disruption (100% in Taiwan).
• US mandate for TSM to transfer advanced packaging to Arizona, leading to yield/cost deterioration.

Rebuttal :

• Amkor $7B Arizona Plant: To commence production in 2026, capable of handling 30-40K wpm CoWoS back-end processes (vs. complementing TSM's Arizona fab).
• ASE Mexico/Malaysia Capacity: Diversifies back-end assembly risk.
• Geopolitical Risk Is Priced-in: TSM's current P/E of 20x vs ASML's 35x partially reflects a Taiwan risk discount.

Should a Taiwan Strait conflict occur, the global AI supply chain would be paralyzed for 6-12 months, but TSM would still be the ultimate recoverer (vs. Samsung/Intel, which would also be impacted + have technological disadvantages), leading to an increase in its long-term market share.

13.9.3 Bearish Argument 3: NVIDIA Builds Its Own Packaging Facilities

Argument :

• NVIDIA acquires packaging equipment manufacturers or builds its own CoWoS production lines (similar to Apple's in-house chip development).
• By 2028, NVIDIA's share drops from 60% to 0%, halving TSM's advanced packaging revenue.

Rebuttal :

• Capital Obstacles: Building 60K wpm CoWoS capacity requires $6-12B CapEx + $2-3B/year operating costs, vs. outsourcing to TSM for $9-10B/year in packaging fees, resulting in a negative 5-year IRR.
• Time Cost: In-house construction would take 3-5 years, causing NVIDIA to miss two generations of products, Rubin/Rubin Ultra ($200B+ revenue opportunity).
• Yield Risk: TSM achieved 85% CoWoS yield in 9 years; NVIDIA starting from scratch might only reach 70% in 5 years, incurring $2-3B/year in defective product losses.

Apple designed its M1 chip in 2020 but still used TSM for manufacturing + InFO packaging, affirming that "design independence ≠ manufacturing independence." NVIDIA is more likely to deepen its ties with TSM rather than build its own facilities.

13.10 Investment Implications and Decision Anchors

13.10.1 Three Certainties in CoWoS Economics

1. Technological Moat Unsurpassable for 3-5 Years

   • TSM leads Samsung by 15 ppt in yield, has 6.5x the capacity, and a 2-generation customer ecosystem gap.
   • SoIC 3μm vs. competitors' 10μm; mass production in 2027 will widen the gap.

2. Customer Lock-in Effect Strengthened

   • NVIDIA/Broadcom/AMD have signed multi-year agreements, locked in at least until 2027.
   • New customers (Apple/Intel) joining the SoIC ecosystem, increasing customer stickiness from 3 years to 5+ years.

3. Pricing Power Upward Channel Opens

   • Supply-demand gap of 15-20% continues until 2026, giving TSM room for price increases.
   • NVIDIA's gross margin of 75%+ allows it to absorb CoWoS price hikes without impacting profitability.

13.10.2 Uncertainties and Monitoring Indicators

13.10.3 How to Apply in Valuation

Suggested SOTP Weight Adjustment :

• Increase Weight of Advanced Packaging Segment: From 10% in traditional models to 15% in new models (reflecting SoIC's potential).
• AI Ecosystem Closed-Loop Multiple: 25x P/E (vs. industry average 18-20x), a 25% premium.
• Downside Protection: Even if AI demand halves, CoWoS would still contribute $6-8B revenue × 55% gross margin × 18x P/E = $59.4-79.2B market cap (accounting for 7-8% of total market cap, manageable risk).

Sensitivity Analysis Recommendations:

Chapter 14: SOTP and OVM Valuation

14.1 Step 1: Business Segment Identification and Revenue Breakdown

14.1.1 Four-Segment Breakdown Framework

Although TSMC's financial reports only disclose a single wafer foundry business segment, its business can effectively be broken down into 4 valuation units along three dimensions: technology node + packaging + geography.

Summation Check: 2,694 + 423 + 693 = 3,810 vs Total Revenue 3,849, deviation is only -1.0%, within ±5% acceptable range.

14.1.2 Segment Revenue Derivation Process

Advanced Logic Foundry (N3/N5/N7):

• Q4 2025: N3 accounts for 28% + N5 accounts for 35% + N7 accounts for 14% = 77% Wafer Revenue
• FY2025 Full Year: N3 accounts for 24% + N5 accounts for 35% + N7 accounts for 14% = 73%, deducting ~3% embedded packaging revenue, pure logic foundry is ~70%
• Revenue = 3,849 × 70% = NT$2,694B

Advanced Packaging (CoWoS/InFO/SoIC):

• Q3 2024 Packaging Revenue $3.2B/quarter (QoQ growth +36%)
• FY2025 Packaging Share ~7-9% existing revenue + Test/Packaging support estimated ~11%
• Revenue = 3,849 × 11% ≈ NT$423B

Mature Node Foundry (16nm+):

• FY2025: 16nm accounts for 15% + 28nm and above accounts for 15% = 30%, but ~12% of this belongs to specialty processes (RF/BCD/HV) which requires deducting packaging
• Pure mature foundry ~18%, Revenue = 3,849 × 18% ≈ NT$693B

14.2 Step 2: Segment-by-Segment Valuation

14.2.1 Segment A: Advanced Logic Foundry — P/E×EPS Method

Valuation Logic: TSMC's advanced processes have no direct comparable companies (monopoly), using the Historical P/E Range + Growth Adjustment method.

Key Assumptions:

• FY2026E Advanced Logic Foundry Revenue: NT$3,464B (= 4,945 × 70%)
• Advanced Foundry Net Margin: ~48% (Higher than group's 45.1% due to higher profitability of advanced processes)
• Advanced Foundry Net Income: 3,464 × 48% = NT$1,663B
• Advanced Foundry EPS Contribution: 1,663 / 5,186M = NT$320.7/share
• ADR Equivalent EPS: 320.7 × 5 / 32.8 (TWD/USD exchange rate) = $48.9/ADR

Valuation Multiple Selection:

• TSM Historical 5-year P/E Range: 15-30x, median ~22x
• Current TTM P/E: 28.5x
• Morningstar FVE Implied FY2026 P/E: $428 / FY2026E EPS ~26x
• Analyst Consensus P/E: ~21.4x (Fwd P/E)
• AI Super Cycle Premium: Advanced foundry business enjoys L1×S2 premium of 10-20%

Selected P/E: 23x (Based on analyst consensus 21.4x + AI premium 8%)

Advanced Foundry Valuation: $48.9 × 23x = $1,124.7/ADR Equivalent → Corresponds to the 70% value segment

14.2.2 Segment B: Advanced Packaging — EV/Revenue Method

Valuation Logic: CoWoS is a high-growth business (+45% YoY), not yet independently listed, so the EV/Revenue multiple is more appropriate.

Key Assumptions:

• FY2025 Advanced Packaging Revenue: NT$423B ≈ $12.9B USD
• FY2026E Growth Rate: +40-50% (CoWoS expanding from 80K to 130K wpm)
• FY2026E Packaging Revenue: ~$18.1B USD
• Advanced Packaging TAM 2030: $79.4B (Global advanced packaging market)
• TSM Advanced Packaging Market Share: ~50-60%

Comparable Valuation:

• ASE Technology (日月光): TTM EV/Revenue ~1.2x (Traditional OSAT, low growth)
• High-Growth Packaging Business Premium: Benchmarking against high-growth semiconductor equipment companies at 3-5x Revenue
• Selected EV/Revenue: 4.0x (Reflecting CoWoS's monopolistic position + high growth + AI-driven)

Advanced Packaging EV: $18.1B × 4.0x = $72.4B → /share = $72.4B / 1,037.2M ADR = $69.8/ADR

14.2.3 Segment C: Mature Node Foundry — Comparable P/E Method

Valuation Logic: Using UMC/GFS as comparable companies.

Key Assumptions:

• FY2025 Mature Node Revenue: NT$693B ≈ $21.1B USD
• Mature Node Net Margin: ~25% (Lower than advanced processes, but higher than UMC overall)
• Mature Node Net Income: $21.1B × 25% = $5.3B
• Mature Node EPS: $5.3B / 1,037.2M ADR = $5.1/ADR

Comparable Multiples:

• UMC Current P/E: 18.6x, Fwd P/E: 13.2x
• GFS Current P/E: 30.4x, Fwd P/E: 22.4x
• Selected P/E: 15x (Midpoint of UMC, TSMC's mature nodes have technological advantages but lower growth)

Mature Node Valuation: $5.1 × 15x = $76.5/ADR

14.2.4 Segment D: Overseas Fab Incremental Value

Valuation Logic: Overseas Fabs have a dual impact on valuation -- (1) Short-term gross margin dilution, (2) Long-term premium from a narrowing geopolitical discount.

Short-term Cost Impact (2025-2028):

• Overseas fab operating cost premium: +10% per wafer
• Gross margin dilution: 2-4% (TSMC Q2 2025 earnings guidance)
• Profit impact: 3,849B × 3% (midpoint dilution) = -NT$115B/year → -$3.5B
• NPV (5-year dilution, WACC 9%): -$3.5B × 3.89 (annuity factor) = -$13.6B → -$13.1/ADR

Long-term Value (2028+):

• CHIPS Act Subsidies Total Value: ~$28B
• Geopolitical Discount Narrowing: Current Taiwan Strait risk discount estimated at 10-15%
• Capacity created by $100B Arizona investment: 100K+ wpm by 2030
• Customer Supply Chain Security Premium: ASP increase 3-5%

Overseas Fab Net Incremental Value: Subsidies $28B + Long-term Premium (probability weighted) - Short-term Dilution

• Subsidies NPV: $28B × 0.85 (discount factor) = $23.8B → $22.9/ADR
• Long-term Premium: Addressed in the OVM section (option-like nature)
• Short-term Dilution: -$13.1/ADR
• Net Increment: $22.9 - $13.1 = +$9.8/ADR

14.3 Step 3: Three-Scenario Matrix

Probability-Weighted SOTP:

• Bear (25%): $996 × 25% = $249.0
• Base (50%): $1,282 × 50% = $641.0
• Bull (25%): $1,591 × 25% = $397.8
• Probability-Weighted = $1,287.8/ADR...

Hold on, this figure is clearly unreasonable -- the current share price is only $355. Where's the problem?

Correction Note:

The above segment valuations have a double-counting issue -- the "standalone valuation" for advanced logic foundry was derived using PE×EPS, but Segment A's $48.9 EPS is a theoretical value assuming the segment could operate independently with a 48% net margin. When the three segments are considered as a whole, a consistent methodology is required:

Correction Method: Unified EPS Allocation Method

TSM FY2026E Total EPS: NT$444.3 = $67.7/ADR (= 444.3 × 5 / 32.8)

The issue here is: the segment valuation method applies to EV (Enterprise Value), not direct multiplication by PE to derive share price, because PE×EPS is already market capitalization per share, and the sum of PE×EPS for the three segments ≠ total PE×total EPS (unless the PEs are identical).

Correct SOTP Valuation Framework (EV Method):

Convert all to EV basis:

Segment A: Advanced Logic Foundry EV

• FY2026E Segment EBITDA: Revenue NT$3,464B × EBITDA Margin 55% = NT$1,905B ≈ $58.1B
• EV/EBITDA Multiple: 20x (AI Premium + Monopoly Status)
• Segment EV: $58.1B × 20x = $1,162B

Segment B: Advanced Packaging EV

• FY2026E Segment Revenue: ~$18.1B
• EV/Revenue: 4.0x
• Segment EV: $18.1B × 4.0x = $72.4B

Segment C: Mature Nodes EV

• FY2026E Segment EBITDA: Revenue NT$890B(=4,945×18%) × EBITDA Margin 35% = NT$312B ≈ $9.5B
• EV/EBITDA: 10x (UMC Comparable 8-12x Midpoint)
• Segment EV: $9.5B × 10x = $95B

Segment D: Overseas Fab Incremental EV

• CHIPS Act Subsidies NPV: $23.8B
• Short-term Dilution NPV: -$13.6B
• Segment Net EV: +$10.2B

14.3.1 SOTP-EV Summary

Step 3 Revised Three Scenarios:

Probability-Weighted: $263×25% + $343×50% + $430×25% = $345/ADR

14.4 Step 4: Extreme Stress Test

14.4.1 Scenario A: Taiwan Strait Conflict Leading to Production Interruption (Probability <5%)

• Taiwan's capacity accounts for >85% of TSM's total capacity
• In a conflict scenario, Taiwan fabs completely halt production, overseas fabs only 20K wpm → Revenue drops to approximately 10-15%
• Extreme Scenario Valuation: Overseas Fab Net Assets + IP Value ≈ $150-200B → $145-193/ADR
• Current Price vs Extreme Low: +84-145% → Although the margin of safety appears sufficient, in this scenario, the global semiconductor supply chain collapses, and the valuation framework itself becomes invalid

14.4.2 Scenario B: AI Demand Bubble Burst (Probability 10-15%)

• AI-related revenue drops from 58% to 30%, returning to FY2023 levels
• Advanced node ASP falls by 20%, capacity utilization drops from 95%+ to 70%
• Gross margin falls below 50%
• Extreme Scenario Valuation: PE falls back to 18x × FY2026 Adjusted EPS $45 = $180-210/ADR
• Current Price vs Extreme Low: +69-97% → Sufficient margin of safety

14.5 Step 5: Cross-Verification

Weighted Fair Value: $343×35% + $162×10% + $406×25% + $428×15% + $348×15% = $353/ADR

Deviation Check:

• SOTP vs DCF: $343 vs $162 = +112% → Significant deviation! → Triggers OVM (SOTP itself is close to market price, but FMP DCF is extremely conservative)
• SOTP vs Current Price: $343 vs $355 = -3.4% → Essentially Fair
• Traditional valuation weighted $353 vs Market Price $355: -0.6% → Essentially fair valuation under traditional framework

OVM Trigger Confirmation: FMP DCF $162 < 50% of Market Price $355 (=$177.5) → Mandatory OVM

However, note: Our SOTP $343 is already close to the market price, implying that market pricing is primarily supported by traditional businesses, with limited contribution from option value (unlike TSLA/PLTR). OVM still needs to be performed to identify sources of additional upside.

14.6 Step 6: OVM Option Valuation (v1.0)

14.6.1 OVM-1: Core vs Option Separation

Classification Description:

• Current 80K wpm CoWoS capacity revenue is already included in Core SOTP; The Option portion is incremental revenue from 130K→200K+ wpm expansion + new business from SoIC commercialization in 2027
• NPV of overseas Fab CHIPS subsidies is already included in Core; The Option portion is customer supply chain security premium + long-term revaluation from narrowing geopolitical discount
• DTCO and NanoFlex/A16 are pure options with no independent revenue currently

14.6.2 OVM-2: Reverse DCF (Market Implied Expectations)

Core Question: What growth expectations does the current $355/ADR price in?

Input Parameters:

• Current ADR Price: $355
• Market Cap: ~$368B USD (1,037.2M ADR × $355)
• FY2025 FCF: NT$1,098B ≈ $33.5B
• WACC: 9.0% (Midpoint between Alpha Spread's 7.9% and academic research's 12.6%)
• Terminal Growth Rate: 3.0% (long-term semiconductor growth rate)

Reverse Calculation:

Terminal Value Formula: Terminal Value = FCF_terminal / (WACC - g)
Current Market Cap = Σ[FCF_t / (1+WACC)^t] + TV / (1+WACC)^n

Assuming high growth continues for 5 years (2026-2030), then enters terminal growth:

• Market Cap $368B = FCF_2025 × (1+g_high)^1/(1.09)^1 + ... + FCF_2030/(WACC-g)/(1.09)^5

Solving for: Implied 5-year FCF CAGR ≈ 19.3%

Verification: Analyst Consensus FCF Growth Rate:

• FY2026E: FCF approx. $45B (+34%)
• Actual FY2026E OCF estimate: NT$3,000B+, CapEx NT$1,800B+, FCF ~NT$1,200B ≈ $36.6B (+9.3%)
• FY2027-2030E: FCF growth rate gradually slows to 5-8%

Reverse DCF Conclusion: Market implied expectations Reasonable

14.6.3 OVM-3: Option Tree Pricing

Option 1: CoWoS/SoIC Monopoly Premium Expansion

Option 2: Overseas Fabs Geopolitical Discount Narrowing

Option 3: AI Chip Design Services (DTCO)

Option 4: NanoFlex/A16 Emerging Technology Monopoly

14.6.4 OVM-4: TAM Ceiling Analysis

Total Bull Scenario Maximum Value:

Optionality Utilization Rate: $355 / $600 = 59.2%

Assessment: 40-60% range → "Market pricing for moderate option success rate; need to confirm if option probabilities are supportive"

The current $355/ADR pricing values 59.2% of the TAM ceiling, implying the market believes approximately 2-3 of the four options will partially succeed. Considering TSM's execution capability and the certainty of AI demand, this utilization rate is in the reasonably upper range. If all options materialize according to the Base scenario, the Full Value is approximately $396; if market expectations become even more optimistic, there is still ~$200/ADR of theoretical upside potential to $600.

14.6.5 OVM-5: Narrative Tracking Matrix

Evidence/Counter-Evidence Details:

Narrative A: "AI Unlimited Demand" (Net +4.5, Strong)

• Evidence: NVIDIA CoWoS demand exceeds supply by 15-20% (+1.5) | FY2025 HPC revenue 58% and still accelerating (+1.0) | All 4 major cloud providers use TSM advanced processes for in-house developed chips (+1.0) | FY2026E consensus +28.5% growth rate (+1.0) | CoWoS capacity doubling plan (+1.0) | CFO confirms AI CapEx guidance of $38-42B (+1.0)
• Counter-Evidence: AI ROI questionable (Sequoia "AI $600B Problem") (-1.0) | China's AI chip self-sufficiency accelerating (-1.0) | Global economic slowdown may curb AI spending (-0.5) | Inference chips may not require the most advanced process technology (-0.5)

Narrative B: "Geopolitical Diversification" (Net +2.0, Medium)

• Evidence: Arizona yield 92% exceeds Taiwan mother fab (+1.5) | $100B additional investment commitment (+1.0) | CHIPS Act $6.6B+$5B already implemented (+1.0) | JASM upgraded to 3nm (+1.0) | ESMC Germany project progressing (+1.0)
• Counter-Evidence: Overseas costs +10%/wafer (-1.0) | Gross margin dilution 2-4% (-1.0) | US policy uncertainty (-0.5) | Difficulty in recruiting overseas talent (-0.5) | Taiwan still accounts for 85%+ capacity (-0.5)

Narrative C: "Foundry 2.0 Full-Stack Services" (Net +1.0, Weak)

• Evidence: OIP 500+ partners (+1.0) | A16 backside power delivery industry-first (+1.0) | 3DFabric ecosystem expansion (+1.0)
• Counter-Evidence: DTCO not yet independently charged (-1.0) | Subtle relationship with EDA vendors (-0.5) | "Design + Manufacturing" integration may cause customer concerns (-0.5)

Narrative Risk Indicators:

• Narrative Concentration: Option 1 (CoWoS) accounts for 54% of total option value → Medium concentration risk, but mainly driven by the "AI Unlimited Demand" narrative, which has the highest strength.
• Narrative Rotation Frequency: Dominant narrative stable over the past 12 months (AI demand consistently the main theme), rotation count = 1 (shifted from "Geopolitical Risk" to "AI Boom") → Stable
• Narrative-to-Fundamentals Decoupling Degree: Low — AI narrative supported by strong financial data (FY2025 revenue +33%, HPC contribution 58%)

14.6.6 OVM-6: Option Decay Calendar

Recent Milestones: Option 1 CoWoS 130K wpm (2026-Q4) + Option 2 Arizona Fab 2 equipment move-in (2026-Q3)

• If Option 1 (representing 54% of total option value) SoIC commercialization completely fails → Triggers KS re-evaluation
• KS-OVM-1: "CoWoS/SoIC Milestone Failure — Advanced Packaging Growth Thesis Impaired"

14.7 OVM Summary + Full Value

14.8 Final Valuation Methodology Summary (Including OVM)

Calculations:

• Full Value = Weighted Core + Weighted Options
• Weighted Core = SOTP $343 × 40% + DCF $162 × 5% + Analyst Consensus $406 × 25% + Morningstar $428 × 15% + Historical $348 × 15%
  = $137.2 + $8.1 + $101.5 + $64.2 + $52.2 = $363.2
• OVM Options: $52.7 (Probability & discount-adjusted, added directly)
• Full Value = $363 + $53 = $416/ADR

However, this overlaps with analyst consensus $406 / Morningstar $428 (their valuations may already partially include growth expectations = partial options).

Final Conservative Valuation: Taking the midpoint of Core-only Weighted $363 and Core+OVM $416:

• Fair Value Range: $363 - $416/ADR
• Midpoint: $390/ADR (vs. Market Price $355, Upside approx. +9.9%)

Chapter 15: DCF Valuation Model

15.1 Capital Asset Pricing Model (CAPM) — Cost of Equity

Parameter Derivation:

Ke Sensitivity Analysis:

15.2 Cost of Debt (Kd)

15.3 Capital Structure and WACC

15.4 WACC Summary

15.5 FCF Forecast Model (FY2026-2035)

15.5.1 Revenue Growth Assumptions

Methodology: FY2026-2029 leverages analyst consensus anchors (22 analysts covered), FY2030-2035 employs a self-built decreasing model based on semiconductor cyclicality + AI penetration ceiling.

Revenue Growth Path:

15.5.2 Profitability Assumptions

Profitability Dilution Logic Chain:

15.5.3 CapEx and Depreciation Assumptions

CapEx Return Analysis:

15.5.4 Working Capital and FCF Derivation

FCFF Derivation Logic:

• EBIT = Revenue × Operating Margin (See 2.2 for each year)
• EBIT(1-t) = EBIT × (1 - 16%)
• Change in NWC = (Incremental Revenue) × 1-2%
• FCFF = EBIT(1-t) + D&A - CapEx - Change in NWC

15.6 Terminal Value Calculation and Enterprise Value

15.6.1 Gordon Growth Model (GGM)

15.6.2 Exit Multiple Cross-Verification

Using Blended Terminal Value:

15.6.3 DCF Valuation Summary

Important Revisions:

Revised DCF (Pure GGM):

15.7 Sensitivity Analysis

15.7.1 WACC × Terminal Growth Rate Matrix (Per ADR, USD)

Implied Market Assumptions Back-calculation: [Formula Derivation: If assuming the current price of $355 is fair, back-calculating implies WACC ~14.2% (when g=3.5%) or g = -2% (when WACC=9.65%). Both are unreasonable, indicating that the current price includes an unquantifiable "Taiwan discount."]

15.7.2 Separation of Taiwan Geopolitical Discount

15.8 Bull Case (25% Probability)

15.8.1 Scenario Definition

Core Narrative: The AI super cycle extends beyond 2030, with TSMC being the only foundry capable of mass producing sub-2nm nodes, enjoying sustained pricing power and tight capacity. Geopolitical risks are significantly reduced due to overseas fab expansion.

15.8.2 Bull Case Key Assumptions